Semiconductor Memory Verification Voltage Segmentation
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Solution Overview
Problem
The performance of semiconductor memory devices deteriorates as the number of verification operations increases, leading to inefficiencies in data storage and retrieval processes.
Innovation Solution
A semiconductor memory device configuration that includes a first bit line, a second bit line, a source line, and a word line, with a voltage generation circuit and row decoder to optimize verification operations by applying specific voltages during verification, reducing the number of verification times and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of values increases to enhance storage capacity, then the storage capability is improved, but the number of verification times increases leading to performance deterioration
Solution Approach 1:
The patent segments the verification process by applying different voltages to different bit lines (first bit line with first voltage, second bit line with second voltage) to simultaneously verify multiple values. This divides the verification task into parallel operations, reducing the total number of verification cycles needed while maintaining multi-value storage capability.
Solution Approach 2:
The patent implements periodic verification actions with varying voltage levels applied to bit lines in different cycles. By periodically switching voltage levels on different bit lines, the system can verify multiple threshold voltage levels (and thus multiple stored values) in a structured sequence that reduces overall verification time compared to sequential verification of each value.
2Reliability
If multiple verification operations are performed sequentially to ensure data accuracy, then the reliability is improved, but the write operation period is extended
Solution Approach 1:
The patent merges multiple verification operations into a single cycle by simultaneously applying different voltages to different bit lines. The voltage generation circuit applies first voltage to first bit line and second voltage to second bit line in parallel, combining what would traditionally be sequential verification steps into one concurrent operation, thus maintaining reliability while shortening the write operation period.
Solution Approach 2:
The patent performs preliminary voltage application to bit lines before the actual verification read operation. By pre-applying the appropriate voltages to different bit lines based on which values need verification, the system prepares the verification state in advance, allowing the actual data read and comparison to happen more efficiently and reducing the total write operation duration.
Data Source
AI summary
A semiconductor memory device includes: a first bit line connected to a first string including memory cell transistors; a second bit line connected to a second string including memory cell transistors; a source line connected to the first string and the second string; a word line connected to gates of the memory cell transistors in same rows of the first and strings; a voltage generation circuit configured to apply a first voltage to the first bit line according to a first target level, apply a second voltage to the second bit line according to a second target level, and apply a third voltage to the source line; and a row decoder configured to apply a fourth voltage to the word line to which a first memory cell transistor of the first string and a second memory cell transistor of the second string are connected during a verification operation.