Memory Device Verify Voltage Interval Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in reducing distribution degradation during program operations, particularly in omitting verify operations in subsequent loops, which affects the efficiency and accuracy of data programming.
Innovation Solution
A memory device and method that adjust the verify voltage interval between two verify voltages based on a predetermined target loop, allowing for the omission of verify steps in specific loops (n+1) and (n+2) by applying different bit line voltages to memory cells with varying threshold voltages, thereby optimizing program operations and reducing distribution degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify operations are performed in all loops during program operation, then programming accuracy is maintained, but operational time increases and efficiency decreases
Solution Approach 1:
The patent applies partial verify operations only in specific loops (n+1) and (n+2) rather than performing verify operations in all loops. The verify voltage interval is adjusted to a target interval in these specific loops based on threshold voltage distribution characteristics, providing sufficient verification where needed while reducing unnecessary verification operations in other loops, thus balancing accuracy and efficiency
Solution Approach 2:
The patent dynamically adjusts the verify voltage interval parameter based on the loop stage and threshold voltage distribution. In loops (n+1) and (n+2), the verify voltage interval is changed to a target interval that is smaller than the default interval, allowing for more precise verification when threshold voltage distribution is critical, while using default interval in other loops to reduce operational time
2Device complexity
If a single verify voltage interval is used in all loops, then device complexity is reduced, but programming precision deteriorates due to distribution degradation
Solution Approach 1:
The patent implements dynamic adjustment of the verify voltage interval based on the program loop stage and threshold voltage distribution characteristics. The verify voltage controller changes the verify voltage interval from a default interval to a target interval in specific loops (n+1) and (n+2), adapting the verification precision to the actual state of memory cell programming, thus maintaining high programming precision without requiring overly complex static control mechanisms
Solution Approach 2:
The patent segments the program operation into different phases with different verify voltage interval strategies. The first phase uses a default verify voltage interval, while the second phase (loops n+1 and n+2) uses a target verify voltage interval. This segmentation allows the system to apply appropriate verification precision to each phase, improving overall programming precision while managing device complexity
3Manufacturing precision
If verify voltage interval is adjusted based on threshold voltage distribution, then programming accuracy is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent employs feedback mechanisms where the verify voltage controller monitors the program loop stage and threshold voltage distribution characteristics, then adjusts the verify voltage interval accordingly. The program operation controller receives feedback from the peripheral circuit about programming progress and uses this information to determine when to switch between default and target verify voltage intervals, improving programming accuracy through adaptive control without requiring overly complex external control systems
Data Source
AI summary
A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation including a plurality of loops each including a program voltage apply step and a verify step by using a plurality of verify voltages; and a program operation controller for controlling the peripheral circuit to perform the program operation. The program operation controller includes: a verify voltage controller for changing a verify voltage interval as an interval between the plurality of verify voltages from a predetermined target loop among the plurality of loops; and a bit line voltage controller to control bit line voltages applied to bit lines connected to first memory cells and second memory cells in the program voltage apply steps of an (n+1)th loop and an (n+2)th loop, based on a verify result in the verify step of an nth loop among the plurality of loops.