Memory Cell Array Via Layout for Uniform Vertical Integration
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving uniformity and reducing size, particularly in the integration of memory cells and logic circuits in vertical memory devices with PUC structures, where the integration of more memory cells within the same area is hindered by the layout and spacing of via regions and block selection units.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with via regions and block selection units arranged in a specific direction, where the width of via regions corresponds to a multiple of the cell unit width, and the interval between adjacent via regions corresponds to a multiple of the block selection unit width, optimizing the layout to enhance integration and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If via regions are arranged with standard spacing in vertical memory devices, then signal transmission is enabled, but device size reduction and uniformity are compromised
Solution Approach 1:
The via regions are segmented into multiple via holes arranged in a matrix pattern within each via region. This segmentation allows the via regions to be distributed more uniformly across the device while maintaining functional signal transmission paths, thereby improving manufacturing precision and uniformity without excessive layout complexity
Solution Approach 2:
Multiple via holes are merged within each via region to form a functional unit. The via regions themselves are merged with the memory cell array structure, with via regions positioned at intersections of word lines and bit lines, creating a unified layout that improves uniformity while managing complexity
2Quantity of substance
If more memory cells are integrated within the same area using PUC structure, then integration density increases, but layout uniformity and signal transmission efficiency deteriorate due to via region spacing
Solution Approach 1:
The via regions are extended into the vertical dimension with multiple via holes stacked in the vertical direction. This dimensional change allows increased integration density by utilizing vertical space while maintaining uniform horizontal distribution of via regions, thus improving both integration density and layout uniformity
Solution Approach 2:
Multiple via holes are nested within each via region, creating a hierarchical structure. This nesting allows more memory cells to be integrated within the same area by efficiently utilizing the vertical space within each via region, thereby increasing integration density while maintaining uniform layout through regular spacing of the via regions
3Ease of manufacture
If via region width does not correspond to multiple of cell unit width, then layout flexibility is maintained, but manufacturing uniformity and device size optimization are compromised
Solution Approach 1:
The via region width is changed to be an integer multiple of the cell unit width. This parameter change simplifies the manufacturing process by enabling regular, repeating patterns that are easier to manufacture with uniformity, while the optimized spacing reduces the overall device size compared to non-multiple dimensions
Data Source
AI summary
A semiconductor memory device includes a memory cell array disposed over a substrate extending in a first direction and a second direction intersecting with the first direction in a first semiconductor layer, and including a plurality of cell units and at least two via regions that are arranged in the second direction, wherein a width of each of the at least two via regions in the second direction is a multiple of a width of each of the plurality of cell units in the second direction.