Semiconductor Memory Voltage Control Circuit
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the write operation speed due to voltage fluctuations across word lines, leading to delays in program and verify operations.
Innovation Solution
The semiconductor memory device employs a control circuit that executes multiple program loop operations with specific voltage sequences, where a first write voltage is applied to one word line and a series of voltages are applied to adjacent word lines to prevent excessive voltage drops and facilitate equal voltage boosting across all word lines during the verify operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a first write voltage is supplied to a selected word line during a program operation, then the program operation can be executed, but voltage drops occur in adjacent word lines causing delays in verify operations
Solution Approach 1:
The patent applies preliminary action by supplying a first voltage to adjacent word lines during the program operation to prevent voltage drops before they occur. This proactive voltage maintenance ensures that when verify operations are subsequently executed, the adjacent word lines are already in the appropriate voltage state, eliminating delays that would otherwise occur during voltage boosting.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the voltage supplied to adjacent word lines based on the operational phase. During program operations, a first voltage is supplied to maintain appropriate potential; during verify operations, a second voltage is supplied to facilitate rapid verification. This dynamic parameter adjustment optimizes both program and verify operation speeds without mutual interference.
2Reliability
If multiple program loop operations are executed to write data, then data storage reliability is improved, but operation time increases due to sequential program and verify operations
Solution Approach 1:
By maintaining appropriate voltage levels in adjacent word lines during program operations through preliminary voltage application, the patent prepares the system state in advance. This reduces the time required for subsequent verify operations, allowing multiple program loop operations to execute more efficiently while maintaining data storage reliability.
Solution Approach 2:
The patent implements periodic action through alternating program and verify operations in a structured sequence. By optimizing the voltage supply timing and levels during each periodic cycle, the patent enables reliable data storage while minimizing the total duration of write operations through efficient cycling between program and verify phases.
3Device complexity
If voltage is supplied to all word lines equally during program operations, then circuit simplicity is maintained, but voltage fluctuations cause inconsistent operation across different word lines
Solution Approach 1:
The patent applies local quality by providing different voltage levels to different word lines based on their specific operational needs. The selected word line receives a first write voltage during program operations, while adjacent word lines receive a first voltage to prevent drops, and non-selected word lines receive appropriate voltages. This localized voltage control ensures consistent operation across all word lines while maintaining reasonable circuit complexity through systematic voltage management.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first memory cell and a second memory cell arranged adjacent to each other and coupled in series; and a control circuit, wherein the control circuit is configured to: at a time of the program operation in a first program loop operation targeted for the first memory cell, during a first period, while suppling a first write voltage to the first memory cell, supply a first voltage smaller than the first write voltage to the second memory cell, and during a second period, while supplying a second voltage smaller than the first voltage to the first memory cell, supply a third voltage greater than the second voltage to the second memory cell.