3D Memory Voltage Control for Uniform Write Speeds
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in achieving uniform writing and reading speeds due to variations in memory shaft diameters across different rows, leading to non-uniform memory cell characteristics and performance.
Innovation Solution
The semiconductor memory device employs a voltage control mechanism where bit lines connected to memory shafts in different rows are applied varying voltages during writing and reading operations, with specific voltage differences applied based on the position of the memory shafts relative to the insulation separating layer, to ensure uniformity in writing and reading speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are used to achieve high integration, then memory capacity increases, but writing and reading speeds become non-uniform due to variations in memory shaft diameters
Solution Approach 1:
The patent applies different voltages to bit lines connected to memory shafts in different rows based on their positions relative to the insulation separating layer. Memory shafts closer to the insulation separating layer receive different voltage levels than those farther away, compensating for diameter variations and achieving uniform writing and reading speeds across all memory cells
2Quantity of substance
If memory shafts are arranged in multiple rows within the laminated body, then integration density increases, but diameter variations across rows cause non-uniform memory cell characteristics
Solution Approach 1:
The patent changes the voltage parameter applied to bit lines based on the position of memory shafts. By adjusting voltage levels according to row position relative to the insulation separating layer, the patent compensates for manufacturing variations in memory shaft diameters and achieves uniform memory cell characteristics across all rows
Data Source
AI summary
A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.