Memory Cell Voltage Divider Layout for Reliable Near-Memory Compute
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Solution Overview
Problem
Near-memory compute memory devices require high supply voltage for enhanced sampling range and noise resistance, which poses reliability concerns for header circuits due to voltage stress.
Innovation Solution
Implementing stacked transistors as voltage divider circuits and series-coupled transistors within memory cells to maintain voltage within reliable ranges, using N-type and P-type MOS transistors to manage voltage across memory cells, ensuring reliable operation and noise resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high supply voltage is used to enlarge sampling range and reduce noise interference, then computational accuracy and noise resistance are improved, but reliability of header circuits deteriorates due to voltage stress
Solution Approach 1:
The patent divides the voltage distribution function into multiple segments: memory cells use series-coupled transistors for basic voltage division, while header circuits use additional voltage divider circuits with adjustable ratios. This segmentation allows different parts of the system to operate at different voltage levels, enabling high supply voltage for computational accuracy while protecting header circuits through localized voltage division.
2Adaptability or versatility
If high supply voltage is applied to memory cells, then sampling range is enlarged, but voltage stress on transistors increases causing reliability concerns
Solution Approach 1:
The patent dynamically adjusts voltage division ratios in header circuits based on operational requirements. During compute-in-memory operations, voltage dividers are configured to provide larger voltage swings for enhanced sampling range. During read operations, the same circuits adjust to maintain voltages within safe operating limits, preventing transistor breakdown while preserving the ability to utilize high supply voltage benefits when needed.
Data Source
AI summary
A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.