Semiconductor Memory Device Voltage Control for Erase Operations
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently controlling threshold voltages during erase and write operations, leading to potential erroneous writing states due to variations in threshold voltages across memory cells.
Innovation Solution
The semiconductor memory device employs a configuration with multiple conductive layers and semiconductor layers, executing specific voltage supply operations such as single-sided and double-sided erase sequences, and EP write sequences to manage threshold voltages, ensuring they remain within defined ranges to prevent erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage control methods are used during erase and write operations, then device complexity is reduced, but threshold voltage variations cause erroneous writing states
Solution Approach 1:
The voltage control is segmented into multiple independent voltage supply lines, each dedicated to specific conductive layers. This allows independent voltage application to different memory cell groups, enabling precise threshold voltage management during erase and write operations without requiring complex global control circuits.
Solution Approach 2:
Different voltage levels are applied locally to specific conductive layers and memory cell groups based on their operational state. The first and second voltage supply lines provide different voltages to adjacent memory cell groups, creating local voltage quality differences that prevent erroneous writing while maintaining simple overall device structure.
2Measurement precision
If multiple voltage supply lines are used to control threshold voltages, then data storage accuracy is improved, but device complexity increases
Solution Approach 1:
The multiple voltage supply lines serve multiple functions: they control threshold voltages during erase operations, prevent erroneous writing during write operations, and maintain data storage accuracy. This multi-functionality reduces the need for separate control circuits for each operation, thereby limiting the increase in device complexity.
Solution Approach 2:
The voltage control is extended into the vertical dimension with conductive layers stacked in the thickness direction of the substrate. This three-dimensional arrangement allows multiple voltage supply lines to control different layers independently, achieving precise threshold voltage control without proportionally increasing planar device complexity.
Data Source
AI summary
A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.