3D Memory Word-Line Voltage Control for Program Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The program disturb phenomenon during the program operation of semiconductor memory devices, particularly in 3D semiconductor devices, is not effectively addressed by existing technologies, leading to issues with data retention and integrity.
Innovation Solution
A semiconductor memory device design that includes a control logic to vary the potential of the calibration pass voltage applied to the lowermost word line based on the position of the selected page, using a voltage generator to generate program, pass, and calibration pass voltages, and an address decoder to apply these voltages differently to selected and unselected word lines, thereby mitigating the program disturb phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a program voltage is applied to a selected word line during program operation, then data is programmed into memory cells, but program disturb phenomenon occurs in adjacent memory cells
Solution Approach 1:
The patent applies different voltages to different word lines based on their position relative to the selected word line. Specifically, a first voltage is applied to a first unselected word line and a second voltage (different from the first voltage) is applied to a second unselected word line. This local differentiation of voltage levels mitigates the program disturb phenomenon in adjacent memory cells while maintaining efficient program operation on the selected word line.
2Ease of operation
If conventional pass voltage is applied to all unselected word lines, then program operation can be performed, but program disturb phenomenon cannot be effectively mitigated
Solution Approach 1:
The patent introduces a voltage differentiation mechanism where control logic generates different voltages for different unselected word lines based on their positional relationship with the selected word line. The first unselected word line receives a first voltage while the second unselected word line receives a second voltage, creating localized voltage optimization that prevents program disturb without significantly complicating the overall operation.
Data Source
AI summary
Provided herein is a semiconductor memory device. The semiconductor memory device may include a memory block including a plurality of pages, a peripheral circuit configured to perform a program operation on the memory block by respectively applying a program voltage, a pass voltage, and a calibration pass voltage to a plurality of word lines respectively connected to the plurality of pages, and a control logic configured to control the peripheral circuit to vary a potential of the calibration pass voltage to be applied to a lowermost word line connected to a page adjacent to a semiconductor substrate or a source select transistor among the plurality of pages based on a position of a page selected from among the plurality of pages during the program operation.