Nonvolatile Memory Voltage Control for Word Line Setup Time
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Solution Overview
Problem
Nonvolatile memory devices face increased setup times due to parasitic resistance and capacitance variations in word and bit lines, affecting program, read, and verify operations.
Innovation Solution
Implementing a control logic to calculate voltage differences between nodes on word and bit lines, adjusting reference voltage levels based on these differences, and determining target voltage levels to optimize operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is applied to word lines and bit lines in conventional memory devices, then data storage and retrieval operations are enabled, but parasitic resistance and capacitance cause voltage level variations along the lines, increasing setup time and reducing operation speed
Solution Approach 1:
The patent applies preliminary action by pre-calculating voltage drops across word lines and bit lines before actual memory operations. The control logic determines appropriate voltage levels in advance based on line length and load characteristics, ensuring that voltage reaches target nodes within required setup time. This proactive voltage adjustment compensates for parasitic effects before they impact operation speed.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting voltage levels applied to word lines and bit lines based on calculated voltage drops. The system modifies voltage parameters (magnitude and timing) to compensate for parasitic resistance and capacitance variations, maintaining consistent voltage at distant nodes and reducing setup time variability across different memory operations.
2Reliability
If voltage levels are increased to overcome parasitic resistance and capacitance effects, then voltage reaches distant nodes more reliably, but power consumption increases and device reliability decreases due to stress on memory cells
Solution Approach 1:
The patent applies local quality by implementing position-dependent voltage adjustment. The control logic calculates specific voltage drops for each word line and bit line based on their individual characteristics and distances from the voltage generator. Each line receives a customized voltage level tailored to its specific parasitic load, ensuring reliable voltage delivery to distant nodes without uniformly increasing power consumption across the entire memory array.
Solution Approach 2:
The patent implements feedback by using calculated voltage drop information to adjust applied voltage levels. The system measures or estimates voltage variations along word lines and bit lines, then uses this feedback to determine optimal voltage levels that ensure reliable delivery while minimizing excess power consumption. This closed-loop approach prevents both under-volting (which causes failures) and over-volting (which wastes power).
Data Source
AI summary
Provided is a method of operating a nonvolatile memory device including a voltage generator, the method including calculating a difference between a voltage level of a first word line node and a voltage level of a second word line node, changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the voltage levels, and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level. The first word line node may be closer from an output terminal of the voltage generator than the second word line node.