Memory Access Voltage Regulation With Switchable Temperature Coefficients
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Solution Overview
Problem
Existing memory devices face high power consumption and reliability issues due to constant high voltage levels required for word lines, particularly affecting metal-oxide-semiconductor field-effect transistors (MOSFETs) with time-dependent dielectric breakdown properties.
Innovation Solution
A semiconductor device incorporating a temperature coefficient modulation (TCM) circuit that generates output voltages with switchable temperature coefficients, adjusting voltage levels for read and write operations to optimize power management and reduce voltage stress on MOSFETs, using a regulator with a comparator and adjustable resistive elements to manage voltage based on temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constant high voltage levels are applied to word lines, then memory operations can be performed reliably, but power consumption increases and MOSFET reliability deteriorates due to time-dependent dielectric breakdown
Solution Approach 1:
The patent implements dynamic voltage adjustment by switching between different voltage levels (VDD1 for read operations, VDD2 for write operations) based on the operation type. The regulator circuit dynamically changes the voltage supplied to word lines according to temperature conditions and operation mode, avoiding constant high voltage application and thereby reducing power consumption while maintaining operational reliability
Solution Approach 2:
The patent changes the voltage parameter dynamically based on temperature conditions. The TCM circuit detects temperature and adjusts the voltage level accordingly, while the regulator modifies voltage output based on temperature coefficients. This parameter adaptation allows the system to maintain reliable operations across temperature ranges while minimizing power consumption by using lower voltages when conditions permit
2Use of energy by moving object
If voltage levels are reduced to save power, then power consumption decreases, but memory operation reliability may be compromised
Solution Approach 1:
The patent changes voltage parameters adaptively based on temperature conditions and operation mode. The TCM circuit detects temperature and adjusts voltage coefficients, while the regulator modifies output voltage accordingly. This ensures that voltage levels are optimized for each operational context, maintaining reliability when needed while reducing power consumption when conditions allow
Solution Approach 2:
The system implements feedback control through the TCM circuit that monitors temperature and provides feedback to the regulator. This feedback loop ensures that voltage levels are continuously adjusted to maintain optimal operation reliability while minimizing power consumption. The regulator responds to temperature feedback by adjusting voltage output, preventing both under-voltage failures and unnecessary power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TCM circuit enhances power efficiency and reliability by optimizing write and read operations, minimizing power consumption and voltage stress on MOSFETs across a wide temperature range, thereby improving the overall performance of memory devices.
Implementation Method 1
A semiconductor device incorporating a temperature coefficient modulation (TCM) circuit that generates output voltages with switchable temperature coefficients, adjusting voltage levels for read and write operations to optimize power management and reduce voltage stress on MOSFETs, using a regulator with a comparator and adjustable resistive elements to manage voltage based on temperature changes
Data Source
AI summary
A semiconductor device includes: a memory array; a modulation circuit including a first resistive element, a second resistive element and a third resistive element; a regulator including a transistor; and a controller configured to: determine an operation mode of the memory array; generate a first regulated voltage at a drain terminal of the transistor, wherein the first regulated voltage corresponds to a positive temperature coefficient, a negative temperature coefficient or a zero temperature coefficient according to a first resistance ratio between the first resistive element and the second resistive element and a second resistance ratio between the second resistive element and the third resistive element; provide a first access voltage to the memory array in response to the first regulated voltage corresponding to the positive temperature coefficient; and provide a second access voltage to the memory array in response to the first regulated voltage corresponding to the negative temperature coefficient.