Memory Substrate Wiring Layout for Low-Reflection Clock Signals
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Solution Overview
Problem
Existing electronic devices face challenges in downsizing while maintaining waveform integrity due to signal reflection and the need for resistor devices to attenuate reflected signals, which increase mounting area and cost.
Innovation Solution
The electronic device employs a wiring configuration where clock and chip select signals are propagated through different wiring layers based on the memory device's surface location, with optimized distances between adjacent memory devices to minimize signal reflection and improve waveform integrity without using resistor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistor devices are provided to attenuate reflected signals, then waveform integrity is improved, but mounting area increases
Solution Approach 1:
The patent extracts the signal attenuation function from separate resistor devices and integrates it into the wiring structure itself. By forming resistive wirings directly on the substrate, the patent eliminates the need for discrete resistor components while maintaining the signal attenuation effect, thus improving waveform integrity without increasing mounting area.
Solution Approach 2:
The patent merges the function of signal attenuation (previously requiring separate resistor devices) with the existing wiring structure. The resistive wirings are integrated into the signal transmission path, combining the transmission line function with the attenuation function in a single structural element, thereby reducing component count and mounting area.
2Reliability
If more wiring layers are used to separate clock and chip select signals, then waveform integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by providing resistive wirings only in specific locations where signal reflection is problematic. Instead of uniformly increasing wiring layer complexity across the entire device, the patent selectively introduces attenuation structures only in the signal transmission paths where needed, thus improving waveform integrity without proportionally increasing overall device complexity.
Data Source
AI summary
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.