Non-Volatile Memory Word Gate Residue Prevention
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Solution Overview
Problem
The challenge in manufacturing non-volatile memory is the difficulty in removing poly-silicon residues near the corners of the ONO layer, leading to electrical-conductive residues that cause connection issues between word lines and result in memory failures.
Innovation Solution
The solution involves forming conductive spacers before word gates, using dummy bit lines and an electron trapping layer, and a specific manufacturing process that includes ion implantation and dielectric layer formation to prevent residue formation and ensure reliable connections between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If poly-silicon layers are formed and patterned to create word gates, then memory structure is formed, but poly-silicon residues remain near the corners of the ONO layer causing word line connections and memory failure
Solution Approach 1:
The patent applies preliminary action by forming the electron trapping layer and conductive spacers before the word gate poly-silicon layer. This sequence allows the electron trapping layer to be positioned underneath the word gates in advance, creating a structural foundation that prevents poly-silicon residues from causing word line connections. The conductive spacers are also formed beforehand to establish proper spacing and isolation structures before the problematic poly-silicon deposition occurs.
Solution Approach 2:
The patent segments the memory structure into distinct functional layers: the electron trapping layer is separated and positioned underneath the word gates, while conductive spacers are formed as independent structures between word gates and trenches. This segmentation allows each component to fulfill its specific function independently, with the electron trapping layer specifically addressing the residue problem by capturing stray poly-silicon material.
2Productivity
If conventional manufacturing process is used, then production efficiency is maintained, but poly-silicon residues cause electrical connections between word lines
Solution Approach 1:
The electron trapping layer acts as an intermediary element positioned between the substrate and the word gates. This intermediate layer specifically addresses the harmful poly-silicon residues by providing a trapping mechanism that prevents residues from creating unwanted electrical connections. The conductive spacers also serve as intermediaries, providing physical separation and electrical isolation between adjacent word gates and trenches.
3Manufacturing precision
If word gates are formed by etching poly-silicon layer, then memory structure is completed, but residues along ONO layer edges cause connection failures
Solution Approach 1:
The electron trapping layer is formed in advance before the word gate etching process. This preliminary formation ensures that when poly-silicon is etched away to create word gates, any residues left along the ONO layer edges are captured by the pre-positioned electron trapping layer, preventing connection failures between word lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces residue formation during patternization, enhancing memory reliability by preventing electrical connections between word lines and improving overall memory performance.
Implementation Method 1
an ion implantation process 108 is performed upon the substrate 100, so that a lightly doped drain (LDD) area 112 is formed in the substrate 100
Data Source
AI summary
A nonvolatile memory consisting of a substrate, a dielectric layer, word lines, word gates, conductive spacers, electron trapping layer, insulation layer and buried bit lines is provided. The dielectric layer is on the substrate and has several poly trenches thereon, and the word lines are disposed over the substrate across the poly trenches. The word gates are in the poly trenches between the word lines and the substrate, and the conductive spacers are between the word gates and the inner wall of each poly trench. The electron trapping layer is disposed between the conductive spacers and the inner wall of each poly trench and between the conductive spacers and the substrate. The insulation layer is between the conductive spacers and the word gates. The buried bit lines are in the substrate between the poly trenches.