Memory Device Word Line Bridge Defect Detection
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Solution Overview
Problem
As memory devices are miniaturized, word line bridge defects become more likely due to reduced distances between wirings, leading to operational degradation and the need for effective defect detection and remediation methods.
Innovation Solution
A memory device and storage system that utilize an erasing operation to detect word line bridge defects by applying different voltages to word lines during erasing and verification operations, determining the presence of a defect if the erase operation fails, allowing for identification and potential remediation of bridge defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If memory device size is miniaturized, then device integration and density are improved, but word line bridge defects increase due to reduced distances between wirings
Solution Approach 1:
The patent applies preliminary action by performing an erase operation before read operations to detect and remediate word line bridge defects. The erase operation is executed as a preliminary step to clear potential defects that may affect subsequent read operations, ensuring reliable detection without requiring additional complex detection circuits.
Solution Approach 2:
The memory device uses its own erase function to detect word line bridge defects, rather than requiring external detection equipment. The erase operation inherently reveals bridge defects through verification failures, allowing the device to self-diagnose and self-report defects using existing functional operations.
2Reliability
If word line bridge defects occur, then operational performance degrades, but conventional detection methods are insufficient
Solution Approach 1:
The patent implements feedback by using verification operations after erase to detect word line bridge defects. The verification step provides feedback information about the success or failure of the erase operation, which indicates the presence of bridge defects. This feedback mechanism enables continuous monitoring and detection without additional complex testing infrastructure.
Solution Approach 2:
The patent changes operational parameters by applying different voltages to different word lines during the erase operation. By varying voltage application timing and patterns across multiple word lines, the method creates different electrical conditions that reveal bridge defects through verification failures, using parameter variation instead of complex detection circuitry.
3Productivity
If erase voltage is applied to multiple word lines simultaneously, then erasing speed is improved, but word line bridge defects cannot be detected
Solution Approach 1:
The patent segments the erase operation into multiple phases with different voltage application patterns to different word lines. Instead of applying voltage to all word lines simultaneously, the method divides the erase process into sequential or staggered voltage applications, allowing defect detection through verification while maintaining overall erase functionality. This segmentation enables both speed and detection capability.
Solution Approach 2:
The patent uses periodic action by alternating between erase operations with different voltage patterns and verification operations. The method periodically switches between applying erase voltage to different word line groups and performing verification reads, creating a rhythmic pattern of erase-verify cycles that detects defects while maintaining efficient erase throughput through structured periodic operations.
Data Source
AI summary
A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.