Memory Device Word Line Discharge Control for Program Disturb
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in improving reliability and operation speed during program operations, particularly in three-dimensional structures where weak page groups can lead to program disturb phenomena, affecting the integration and efficiency of memory cell programming.
Innovation Solution
A memory device and method that include peripheral circuits and control logic to sequentially or simultaneously discharge word lines based on whether a selected page is in a weak page group, applying program and verify voltages, and counting program loops to optimize the discharge operation, thereby minimizing disturb effects and enhancing reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If word lines are simultaneously discharged during program operation, then operation speed is improved, but program disturb phenomenon occurs in weak page groups affecting reliability
Solution Approach 1:
The patent dynamically adjusts the word line discharge method based on the program operation state. Control logic determines whether to sequentially or simultaneously discharge word lines depending on factors such as program loop count and verify results, allowing the system to optimize between speed and reliability in different operational contexts
Solution Approach 2:
The patent changes the discharge parameter (sequential vs. simultaneous) based on program operation progress. By monitoring program loop counts and verify outcomes, the system switches between discharge modes to prevent program disturb in weak page groups while maintaining high speed in stable conditions
2Reliability
If word lines are sequentially discharged during program operation, then program disturb phenomenon is minimized improving reliability, but operation speed decreases
Solution Approach 1:
The system dynamically selects discharge timing based on real-time program operation status. When program loops exceed a threshold or verify results indicate instability, sequential discharge is activated to ensure reliability; otherwise, simultaneous discharge maintains speed
Solution Approach 2:
The discharge mode parameter is adjusted based on program loop count and verify outcomes. The control logic modifies this parameter to switch between sequential and simultaneous discharge, optimizing the balance between reliability and speed according to operational conditions
3Reliability
If multiple program loops are performed to ensure reliable programming, then reliability is improved, but operation time increases
Solution Approach 1:
The patent implements feedback mechanisms through verify operations after program loops. Control logic monitors verify results and program loop counts, using this feedback to determine when to terminate programming early or continue with additional loops, optimizing the balance between reliability and time
Solution Approach 2:
The system performs program loops adaptively - sometimes fewer than traditional multi-loop approaches when conditions permit, sometimes more when reliability is at risk. The control logic adjusts the number of loops based on verify results and program state, avoiding unnecessary repetition while ensuring adequate programming
Data Source
AI summary
An embodiment relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of pages respectively corresponding to a plurality of word lines, peripheral circuits configured to apply operation voltages to the plurality of word lines and sequentially discharge or simultaneously discharge the plurality of word lines during a program operation, and control logic configured to control the peripheral circuits to sequentially discharge or simultaneously discharge the plurality of word lines based on whether a selected page among the plurality of pages is included in a weak page group during the program operation.