Non-Volatile Memory Word Line Discharge Control
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Solution Overview
Problem
Current non-volatile semiconductor storage devices, such as NAND flash memory, face challenges in increasing capacity and reducing read time due to limitations in their three-dimensional structure and discharge mechanisms.
Innovation Solution
The implementation of a non-volatile semiconductor storage device with a three-dimensionally stacked memory cell array and a dual potential selection circuit system, which includes a CG driver and a high voltage switch, allows for individual control and discharge of word line potentials, enhancing capacity and reducing read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional stacked memory cell array is used to increase capacity, then storage density is improved, but discharge time increases due to the larger number of word lines
Solution Approach 1:
The patent divides the word line discharge function into multiple segments by introducing a first discharge circuit for selecting and discharging specific word lines, and a second discharge circuit for discharging all word lines. This segmentation allows targeted discharge of only the necessary word lines rather than discharging the entire array, thereby reducing discharge time while maintaining the high capacity benefits of the three-dimensional stacked structure.
2Speed
If multiple word lines are discharged simultaneously to reduce read time, then operating speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic discharge control by using the first discharge circuit to selectively discharge only the word lines that are currently selected and active, rather than discharging all word lines uniformly. This dynamic approach adjusts the discharge operation to match the actual operational needs, reducing unnecessary power consumption while maintaining fast read speeds by quickly discharging only the relevant word lines.
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.