Semiconductor Memory Word Line Selection Circuit Area Reduction
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Solution Overview
Problem
As NAND flash memory technology advances, the increasing number of word lines and required voltages lead to a significant increase in chip area due to the need for numerous switch circuits and level shifters, which complicates the suppression of erroneous writing and improves reliability, especially with large-scale integration.
Innovation Solution
The semiconductor memory device employs a WL selection circuit with a chunk/zone selection circuit, a lower layer WL selection circuit, and an upper layer WL selection circuit, dividing word lines into zones and groups to reduce the number of switch circuits and level shifters, thereby minimizing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of word lines and required voltages is increased to advance NAND flash memory technology, then memory capacity and performance are improved, but chip area increases significantly due to the need for numerous switch circuits and level shifters
Solution Approach 1:
The patent divides the word lines into multiple groups (first group and second group) and assigns different voltage levels to each group. This segmentation allows the memory device to address more word lines without proportionally increasing the number of voltage generation circuits, as each group shares common voltage lines. The chip is effectively partitioned into regions served by different voltage groups, reducing the overall number of switch circuits and level shifters needed.
Solution Approach 2:
The patent implements a universal voltage generation approach where a single voltage generation circuit provides multiple voltage levels (first voltage and second voltage) that are distributed to different word line groups. This multi-functional voltage system allows the same voltage circuit to serve multiple word line groups, eliminating the need for separate voltage circuits for each group and thereby reducing chip area while maintaining the ability to address a large number of word lines.
2Productivity
If numerous switch circuits and level shifters are added to support more word lines, then memory capacity increases, but device complexity and reliability issues arise
Solution Approach 1:
By segmenting word lines into groups that share common voltage lines, the patent reduces the total number of switch circuits and level shifters required. Instead of having individual voltage control circuits for each word line, the segmented approach allows multiple word lines to share control circuits, thereby simplifying the overall circuit architecture while still supporting high memory capacity.
Solution Approach 2:
The universal voltage generation circuit provides multiple voltage levels that are distributed to different word line groups, allowing a single circuit to perform multiple functions. This multi-functional approach reduces device complexity by eliminating redundant voltage generation circuits and switch networks, while maintaining the capability to address a large number of word lines through efficient voltage distribution.
3Productivity
If more switch circuits and level shifters are used to support increased memory capacity, then more word lines can be addressed, but reliability decreases due to more potential failure points
Solution Approach 1:
The segmentation of word lines into voltage groups reduces the total number of switch circuits and level shifters, thereby reducing the number of potential failure points in the system. By having fewer discrete components, the overall reliability of writing operations improves, as each component represents a potential point of failure. The segmented architecture maintains high memory capacity while improving reliability through component reduction.
Solution Approach 2:
The universal voltage generation circuit that serves multiple word line groups reduces the total component count compared to having dedicated circuits for each word line. This consolidation into fewer, multi-functional components improves reliability by reducing the statistical probability of failures, while still maintaining the ability to address a large number of word lines through efficient voltage distribution and control.
Data Source
AI summary
A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.