Semiconductor Memory Word Line Test Circuit
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Solution Overview
Problem
As semiconductor memory devices integrate more densely, off-leakage due to threshold voltage drops occurs, leading to potential failures during testing and increased test times, especially as the distance between adjacent gates decreases, affecting the reliability of memory cell structures.
Innovation Solution
A circuit for testing word lines is designed with a first and second test signal generator, address predecoders, and specific logic operations to generate and decode test signals, enabling word lines efficiently and reducing unnecessary test time by testing only a subset of lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher integration is achieved by decreasing the distance between adjacent gates, then storage capacity per area increases, but off-leakage due to threshold voltage drops increases
Solution Approach 1:
The patent applies preliminary action by performing word line testing during the wafer test stage before packaging. The test circuit activates word lines in a controlled sequence and monitors for off-leakage conditions, allowing defective memory cells to be identified and sorted early in the manufacturing process. This prevents defective devices from proceeding to packaging and ensures only reliable devices are delivered to customers.
2Reliability
If all word lines are tested to ensure reliability, then detection accuracy improves, but test time increases
Solution Approach 1:
The patent segments the word line testing process into two distinct phases: wafer test and package test. During wafer test, a comprehensive test covers all word lines to detect off-leakage conditions. During package test, only a subset of word lines is tested to confirm reliability. This segmentation allows the patent to achieve high detection accuracy during wafer test while reducing the time required for package test, as only a portion of word lines need to be re-tested after packaging.
Data Source
AI summary
A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode signals and a word line test signal, a first address predecoder configured to output first address information signals having first address information in response to the second test signal and a first address signal, and a second address predecoder configured to output second address information signals having second address information in response to the first test signals and second address signals.