Programmable Memory Word Line Layout for Width Uniformity
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Solution Overview
Problem
Existing EEPROM cell technologies face non-uniformity issues in word line widths due to shifting during patterning, which affects the performance and reliability of memory devices.
Innovation Solution
The formation of word lines between spacers using a self-aligning method, where spacers are placed between floating gates and electrode layers are filled to create word lines, ensuring consistent widths and avoiding shifting-related non-uniformities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used to form word lines, then the manufacturing process is simpler, but the word line width becomes non-uniform due to shifting
Solution Approach 1:
The patent applies preliminary action by forming spacers on the floating gates before forming the word lines. These spacers serve as pre-positioned alignment references that guide the subsequent word line formation process, ensuring that word lines are automatically aligned with the floating gates without requiring high-precision patterning operations. This preliminary structuring eliminates the shifting problem that would otherwise occur during conventional patterning.
Solution Approach 2:
The patent implements self-service through self-aligned fabrication processes where the spacers formed on the floating gates automatically define the position and width of the word lines. The word lines are formed to conform to the spacer geometry, making the alignment process self-correcting and eliminating the need for external alignment adjustments. This self-aligning mechanism ensures uniform word line widths without requiring complex external control systems.
2Manufacturing precision
If self-aligning method with spacers is used to form word lines, then word line width uniformity is improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the memory cell structure into distinct functional segments: floating gates, spacers, and word lines. Each component is formed separately with well-defined interfaces. The spacers act as independent alignment elements that segment the fabrication process into manageable stages, where each stage produces a component with precise dimensions that automatically align with adjacent components.
Solution Approach 2:
The patent uses spacers as intermediary elements that mediate between the floating gates and the word lines. These spacers are formed on the floating gates and serve as intermediate structures that transfer the positional information from the floating gates to the word lines. This intermediary structure simplifies the overall fabrication by providing a clear, well-defined interface that guides the formation of subsequent layers without requiring direct high-precision alignment between floating gates and word lines.
Data Source
AI summary
An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.