Memory Wordline ECC Detection for Failing Array Identification

The patent segments the error detection process into multiple independent syndrome checks across different ECC words within the same wordline. Instead of treating each ECC word independently, the system divides the wordline into multiple segments (ECC words) and applies error detection logic to each segment separately, then combines the results to identify wordline-level failures.

The patent implements a nested error detection structure where multiple levels of error checking are combined. The first level checks individual ECC words for correctable errors using traditional syndrome decoding. The second level nests within this by checking multiple ECC words from the same wordline to detect uncorrectable errors. This nested approach allows the system to detect both correctable and uncorrectable errors without requiring completely separate detection circuits.

The patent merges the error detection results from multiple ECC words that share the same wordline. By combining the syndrome information from multiple ECC words, the system can detect gross errors that affect the wordline. When multiple ECC words from the same wordline exhibit error patterns, the merged analysis identifies this as a wordline-level failure rather than independent bit errors, enabling detection of gross errors that would otherwise be mis-corrected.

The patent implements feedback mechanisms where the detection of errors in one ECC word influences the interpretation of errors in subsequent ECC words from the same wordline. When a correctable error is detected in an ECC word, the system feeds this information back to the wordline error detection logic. If similar error patterns appear in other ECC words from the same wordline, the feedback mechanism triggers a wordline failure identification, preventing mis-correction of gross errors.

The patent applies different error detection and correction strategies to different local contexts within the memory system. For individual ECC words, traditional SEC/DED (Single Error Correction, Double Error Detection) logic is applied. For multiple ECC words sharing the same wordline, a different detection logic is applied that looks for patterns indicating wordline failures. This local quality approach allows the system to maintain high reliability for typical bit errors while also detecting gross wordline errors, without a single approach limiting versatility.

The patent creates a universal error detection framework that handles multiple error types through a unified wordline analysis mechanism. The same detection circuitry that identifies correctable errors in individual ECC words also serves to detect uncorrectable errors when analyzing multiple ECC words from the same wordline. This multi-functional approach allows a single detection system to handle both correctable and uncorrectable errors, as well as bitline and wordline failures, without requiring separate specialized circuits for each error type.