Semiconductor Memory Write Leveling via Internal Phase Comparison

Solution Overview

Problem

Conventional semiconductor memory devices inefficiently secure the domain crossing margin (tDQSS) between data strobe and clock signals, especially in high-frequency environments, due to pad-based phase comparisons that do not reflect actual write operation conditions and result in wasteful time and current consumption during write leveling operations.

Innovation Solution

A semiconductor memory device with internal clock and data strobe signal generation units, a phase comparison unit, and a transfer unit that compares phases during a dummy write command, allowing for coarse and fine adjustments using single and multiple pulses to minimize time and current consumption while securing the domain crossing margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pad-based phase comparison is used between data strobe signal and clock signal, then the domain crossing margin is secured on pad level, but the actual write operation environment is not reflected and the margin is not stably secured within the circuit

Engineering Contradiction:

Improvedomain crossing margin stabilityVSAvoidphase comparison accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent performs phase comparison in advance during a dummy write operation before actual write operations. The internal clock signal and internal data strobe signal are generated and compared during this preliminary dummy write command execution, allowing the system to determine write leveling values that ensure domain crossing margin is secured in the actual write operation environment.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates an internal copy of the write operation environment by generating internal clock and data strobe signals that mirror the actual write path signals. By performing phase comparison on these internal signals during a dummy write command, the system accurately reflects actual write operation conditions without requiring external signal connections.

Inventive Principle:

Principle #26Copying

2Reliability

If phase comparison is performed at every toggling duration of the data strobe signal, then phase alignment is continuously monitored, but time and current are consumed wastefully and write leveling efficiency decreases

Engineering Contradiction:

Improvephase alignmentVSAvoidwrite leveling operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs phase comparison periodically during dummy write operations rather than continuously at every data strobe toggling. The internal clock signal enables phase comparison only during specific dummy write command periods, reducing unnecessary comparisons while still ensuring proper phase alignment is achieved and maintained.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent extracts the essential phase comparison function from continuous operation and isolates it to specific dummy write operation periods. By separating the phase comparison activity from continuous data strobe toggling monitoring, the system performs only necessary comparisons during controlled dummy write cycles, minimizing time and current consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If phase comparison is performed at every toggling duration of the data strobe signal, then phase alignment is continuously monitored, but current consumption increases and write leveling efficiency decreases

Engineering Contradiction:

Improvephase alignmentVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent performs phase comparison periodically during dummy write operations rather than continuously at every data strobe toggling. The internal clock signal enables phase comparison only during specific dummy write command periods, reducing unnecessary comparisons while still ensuring proper phase alignment is achieved and maintained.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent extracts the essential phase comparison function from continuous operation and isolates it to specific dummy write operation periods. By separating the phase comparison activity from continuous data strobe toggling monitoring, the system performs only necessary comparisons during controlled dummy write cycles, minimizing time and current consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8775761B2Semiconductor memory device and semiconductor memory system including the same

Publication Date: 2014.07.08 SK HYNIX INC

AI summary

A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit.