Memory Write Leveling Strobe Window Calibration
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Solution Overview
Problem
In DDR SDRAM systems, the fly-by architecture leads to signal skew during transmission, and existing write leveling methods may fail to accurately align the rising edge of the data strobe signal DQS with the target rising edge of the clock signal CLK due to phase differences caused by varying circuit board layouts and operational environments.
Innovation Solution
The implementation of a write leveling method involving a memory device with a write leveling circuit that sets up a strobe window based on notifications from the memory controller, sampling the clock signal CLK within this window, and prohibiting sampling outside it, ensuring alignment of the data strobe signal DQS with the target rising edge of the clock signal CLK through iterative operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory device uses fly-by architecture for control signal transmission, then the data transmission rate is improved, but signal skew occurs during transmission causing misalignment between clock signal and data strobe signal
Solution Approach 1:
The patent applies preliminary action by performing write leveling calibration before normal memory operations. The memory controller and memory device execute a calibration process that adjusts the phase of the data strobe signal DQS relative to the clock signal CLK in advance, ensuring proper alignment is established before actual data transmission begins. This preliminary calibration eliminates signal skew issues that would otherwise occur during normal operations.
Solution Approach 2:
The patent implements feedback through the write leveling calibration process where the memory device samples the clock signal CLK using the data strobe signal DQS and sends sampling results back to the memory controller. The memory controller uses this feedback information to iteratively adjust the phase of DQS until proper alignment with CLK is achieved. This closed-loop feedback mechanism ensures accurate signal alignment despite variations in circuit board layouts and operational environments.
2Productivity
If the write leveling calibration process is performed without phase window constraints, then the calibration speed is improved, but the rising edge of data strobe signal may align to incorrect rising edge of clock signal
Solution Approach 1:
The patent applies segmentation by dividing the calibration process into distinct phases with a focus on creating a phase window constraint. The calibration process is segmented such that sampling of the clock signal is only permitted within a specific phase window range. This segmentation allows the system to quickly eliminate obviously incorrect phase alignments while maintaining the ability to achieve precise alignment within the constrained window, thus preserving calibration speed while improving accuracy.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the phase window constraint parameters during the calibration process. The phase window is defined by specific phase angle ranges that are constrained to prevent sampling outside the valid alignment region. By changing and constraining these phase parameters, the system ensures that the data strobe signal aligns with the correct rising edge of the clock signal while maintaining efficient calibration convergence.
Data Source
AI summary
An electronic device, a memory device of the electronic device, and a write leveling method of the memory device are provided. The memory device is coupled to a memory controller to receive a data strobe signal DQS and a clock signal CLK. In a write leveling mode, the memory device provides a write leveling function to the memory controller, where the write leveling function includes a plurality of iterative operations. In each of the iterative operations, the memory controller sends a notification to the memory device, and the memory device sets up a strobe window based on the notification. The memory device samples the clock signal CLK based on a phase of the data strobe signal DQS in the strobe window, so as to send a sampling result back to the memory controller. The memory device is prohibited from sampling the clock signal CLK outside the strobe window.