Memory Write Leveling Timing Precision
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Solution Overview
Problem
In semiconductor memory devices, internal write leveling processes often result in timing offsets between data strobe and clock signals that exceed specifications, leading to performance reductions, especially when multiple memory ranks share a bus and undergo timing adjustments due to internal errors like voltage, temperature, and clock rate changes.
Innovation Solution
The internal write leveling process is modified to adjust the write internal cycle value from one clock to half a clock, allowing for finer timing adjustments and maintaining the specified phase relationship between data strobe and clock signals, thereby mitigating out-of-specification timing offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the write internal cycle value is adjusted to half a clock for finer timing adjustments, then the timing precision between data strobe and clock signals is improved, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the write internal cycle value from one clock to half a clock, enabling finer timing adjustments. This changes the temporal parameter of the write operation to achieve better synchronization between data strobe and clock signals while managing the associated complexity through systematic implementation.
2Reliability
If write leveling is performed to adjust timing for data strobe signals, then the reliability of data capture is improved, but the loss of time increases due to additional timing adjustments
Solution Approach 1:
The patent implements preliminary action by performing write leveling adjustments in advance to establish proper timing relationships between data strobe and clock signals. This preliminary timing calibration ensures reliable data capture during subsequent operations, preventing timing-related errors without requiring repeated adjustments.
Solution Approach 2:
The patent uses feedback mechanisms in the write leveling process to monitor and adjust timing relationships between data strobe and clock signals. By continuously monitoring timing offsets and making corrective adjustments, the system achieves reliable data capture while minimizing unnecessary time loss through intelligent, data-driven timing optimization.
Data Source
AI summary
A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.