Memory Write Timing Control for Bounded Fault Metadata Storage
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Solution Overview
Problem
Memory devices face challenges in adjusting write timing to accommodate different memory architectures and operating conditions, particularly when bounded fault compliance is required, leading to inefficiencies in write operations.
Innovation Solution
Implementing adjustable write timing settings, such as fuse or mode registers, to enable or disable bounded fault compliant metadata storage, allowing the memory controller to adjust write timing based on the memory module's architecture, and optionally overriding these settings for higher speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bounded fault compliant metadata storage is enabled, then reliability of metadata storage is improved, but write operation time increases
Solution Approach 1:
The patent implements adjustable write timing settings that allow the memory device to dynamically adapt its write timing parameters based on the enabled bounded fault compliance mode. The write timing control circuit modifies timing parameters to account for the additional metadata storage operations required by bounded fault compliance, resolving the contradiction between reliability improvement and time penalty by making the timing adaptive rather than fixed.
2Reliability
If write timing is adjusted for bounded fault compliance, then metadata corruption risk is reduced, but write operation speed decreases
Solution Approach 1:
The patent changes timing parameters based on the bounded fault compliance configuration. When bounded fault compliance is enabled, the write timing control circuit adjusts timing parameters to provide adequate time for metadata storage operations, reducing metadata corruption risk. The adjustable settings allow optimization between corruption resistance and write speed by selecting appropriate timing parameter values for different operational requirements.
3Adaptability or versatility
If adjustable write timing settings are implemented, then adaptability to different memory architectures is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal timing control mechanism that can operate in multiple modes (bounded fault compliant and non-compliant) through a single adjustable write timing control circuit. This multi-functional approach allows the same hardware infrastructure to serve different memory architecture requirements without duplicating components, thereby improving adaptability while minimizing the increase in device complexity.
Data Source
AI summary
Apparatuses, systems, and methods for adjustable write timing. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. When a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other. When disabled, the metadata may be stored in a single location. A second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.