Memristive Memory Array Write Feedback Control
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Solution Overview
Problem
The variability in resistance levels of memristive memory elements in crossbar memory arrays due to open-loop electrical condition application leads to performance issues such as increased error rates and reduced write cycles, as the circuitry is not aware of the resistive state being set, resulting in inconsistent high and low resistance states across elements.
Innovation Solution
Implementing a closed feedback loop in the writing circuitry that allows awareness of the resistive state of memory elements during writing, enabling precise control by discontinuing the electrical condition once a specific resistance level is reached, thereby reducing variability and enabling multi-level cell memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrical conditions are applied in an open loop configuration to set the state of memristive memory elements, then the writing process is simple and fast, but the resistance levels vary between elements and change after each set operation
Solution Approach 1:
The patent implements a feedback mechanism where the resistance state of each memristive memory element is sensed and fed back to the control circuitry. This allows the system to detect the actual resistance level after each write operation and adjust subsequent write conditions accordingly, ensuring consistent resistance levels across all elements while maintaining high writing speed.
2Device complexity
If electrical conditions are applied without feedback awareness of the resistive state, then the circuitry remains simple, but error rates increase and write cycle limits are reduced
Solution Approach 1:
The feedback loop senses the resistance state of the memristive memory element and provides this information back to the control circuitry. This enables the system to detect and correct writing errors, adjust write conditions for subsequent operations, and thereby reduce reading error rates and extend write cycle limits without significantly increasing circuitry complexity.
Solution Approach 2:
The system uses the output signal from the memristive memory element itself (its resistance state) as feedback to control further writing operations. This self-service approach allows the memory element to inform the control circuitry about its own state, enabling automatic adjustment of write conditions to ensure reliability.
3Productivity
If open loop electrical conditions are used for writing, then the process is fast and simple, but variability in resistance levels prevents multi-level cell storage
Solution Approach 1:
The feedback mechanism enables precise control of the resistance level achieved during each write operation. By sensing the actual resistance state and adjusting the electrical conditions accordingly, the system can reliably create distinct resistance levels corresponding to different data states (e.g., 0, 0.5, 1), thereby enabling multi-level cell storage while maintaining fast write speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides finer control over the resistive states of memory elements, reducing variability and allowing multiple bits to be stored in a single memristive memory element, enhancing the performance and reliability of the memory array by ensuring consistent resistance levels.
Implementation Method 1
A memristive memory element can change the state of its resistance in response to an applied electrical condition such as a voltage or an electric current
Implementation Method 2
The feedback loop allows the writing circuitry to be aware of the resistive state of a memory element as that memory element is being written
Data Source
AI summary
A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.