Memristor Cell Pores for High Density Array Isolation

Solution Overview

Problem

As CMOS components approach their size limit, there is a need for technologies that can increase component density and decrease cost per component in integrated circuits, with existing methods facing challenges in minimizing thermal, chemical, and electrical interference between memristor cells in high-density arrays.

Innovation Solution

The use of pores between memristor cells in a memristor array to minimize interaction, combined with specific materials and manufacturing techniques such as copper damascene for crossbars and the use of gases like nitrogen or argon to enhance thermal and chemical isolation, reduces electrical coupling and thermal interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memristor cells are placed in high-density arrays to increase component density, then the number of components per unit area increases, but thermal and chemical interference between adjacent cells increases

Engineering Contradiction:

Improvecomponent densityVSAvoidthermal and chemical interference

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the continuous membrane structure into discrete, isolated compartments by creating pores between adjacent memristor cells. This segmentation isolates each cell's active region, preventing thermal and chemical interference while maintaining high packing density. The pores act as physical barriers that segment the shared membrane into cell-specific zones.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces pores filled with inert gas or vacuum as an intermediary medium between adjacent memristor cells. This intermediary prevents direct thermal and chemical interaction between cells while allowing the cells to remain in close proximity for high-density integration. The pore filling material acts as a buffer that eliminates harmful inter-cell effects.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If CMOS transistor size is continuously shrunk to increase component density, then the number of components increases, but quantum tunneling effects prevent pitches below 32 nanometers

Engineering Contradiction:

Improvecomponent densityVSAvoidquantum tunneling limitations

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent replaces the conventional CMOS transistor mechanical/electrical system with a memristor-based system that uses ionic migration and electrochemical reactions for switching. This substitution allows for significantly smaller feature sizes (below 32nm) because the memristor mechanism does not suffer from the same quantum tunneling limitations as silicon-based transistors, enabling continued scaling for high-density integration.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Object-affected harmful factors

If pores are created between memristor cells to minimize interaction, then thermal and chemical interference is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improveinter-cell interferenceVSAvoidmanufacturing process complexity

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions during the membrane formation process itself, where pores are created and filled with inert material before the memristor cells are fully assembled and operational. By establishing the pore structure and filling material in advance, during the membrane deposition process, the patent avoids adding complex post-processing steps that would increase manufacturing complexity.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for higher memory density, reduced power consumption, and lower production costs by minimizing thermal and chemical interference between memristor cells, enabling more efficient switching and longer battery life in mobile applications.

Implementation Method 1

The use of pores between memristor cells in a memristor array to minimize interaction, combined with specific materials and manufacturing techniques such as copper damascene for crossbars and the use of gases like nitrogen or argon to enhance thermal and chemical isolation

Methodology Applied

Scientific EffectThermal isolation: Thermal Insulation

Implementation Method 2

The use of pores between memristor cells in a memristor array to minimize interaction, combined with specific materials and manufacturing techniques such as copper damascene for crossbars and the use of gases like nitrogen or argon to enhance thermal and chemical isolation

Methodology Applied

Scientific EffectElectrical isolation: Dielectric

Data Source

PatentUS8921960B2Memristor cell structures for high density arrays

Publication Date: 2014.12.30 HEWLETT PACKARD ENTERPRISE DEV LP

AI summary

A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.