Memristor Non-Volatile Storage Unit Layout Optimization
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) and content addressable memories (CAMs) face issues with soft errors in 6-transistor SRAMs, which are volatile and consume more time and energy, and memristor-based solutions occupy larger chip areas due to layout constraints.
Innovation Solution
A non-volatile storage unit comprising memristors, switches, and a write-data circuit, where memristors are used to store data with fewer transistors, reducing chip area and energy consumption, and appropriate electronic elements are disposed between adjacent memristors to meet layout design rules, optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 6T SRAM is used for configuration elements in PLD, then the device can be programmed and reprogrammed, but the device is affected by soft errors and consumes more energy with longer initialization time
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from volatile SRAM to non-volatile memristor, thereby eliminating soft error susceptibility while maintaining programmability through resistance state changes that persist without power
Solution Approach 2:
The patent substitutes the mechanical/electrical SRAM cell structure with a memristor-based structure that uses electrical resistance changes to store configuration data, replacing the need for continuous power supply and complex refresh circuits
2Duration of action of stationary object
If memristors are used to replace SRAM, then non-volatile storage is achieved, but the chip area increases due to layout spacing requirements
Solution Approach 1:
The patent merges multiple functions into the memristor cell structure, combining storage, switching, and spacing utilization functions. The electronic elements placed in spacing regions serve dual purposes: meeting layout design rules and providing additional circuit functionality, thereby reducing overall chip area
Solution Approach 2:
The patent utilizes the spacing dimension between adjacent memristors productively by placing electronic elements in these regions. This transforms wasted space into functional circuit real estate, effectively increasing area utilization without increasing physical chip footprint
3Manufacturing precision
If appropriate spacing is reserved for adjacent memristors, then layout design rules are met, but the chip area occupied increases
Solution Approach 1:
The patent makes the spacing regions between memristors self-productive by placing electronic elements that utilize these spaces for functional purposes. The spacing requirements, originally imposed as constraints, become opportunities for additional circuit functionality, thereby serving multiple design objectives simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables compact, efficient non-volatile storage with reduced energy consumption and faster initialization, while adhering to layout design rules, thus addressing the limitations of conventional SRAM and memristor-based solutions.
Implementation Method 1
memristors to store data
Data Source
AI summary
A non-volatile storage device adopt memristors to store data and uses fewer transistors to realize the same circuit function, whereby to decrease the chip area and reduce the time and energy spent in initiating the device. Further, the non-volatile storage device disposes appropriate electronic elements in the spacing between adjacent memristors to meet the layout design rule and achieve high space efficiency in the chip lest the space between memristors be wasted.