MEMS Anti-Stiction Bump Formation Sequence
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Solution Overview
Problem
In MEMS-CMOS integration, existing methods for forming anti-stiction bumps result in large sidewall angles and top critical dimensions, leading to increased stiction between the substrate and moveable parts, and also face lithographic challenges such as reduced processing windows and photoresist collapse when attempting to reduce bump size.
Innovation Solution
The method involves forming anti-stiction bumps prior to creating a cavity, using a process sequence that reduces the sidewall angle and top critical dimension of the bumps by etching the substrate in two stages, with a masking layer to define the bumps first and then the cavity, thereby minimizing stiction and avoiding lithographic issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-stiction bumps are formed with conventional methods, then the bumps provide stiction reduction, but the sidewall angle and top critical dimension become too large
Solution Approach 1:
The patent applies preliminary action by forming the anti-stiction bumps before creating the cavity structure. This sequence allows the bumps to be formed with optimized dimensions and sidewall angles independent of the cavity formation process, thereby reducing stiction while maintaining precise dimensional control without the constraints of subsequent cavity etching
Solution Approach 2:
The patent segments the formation process into distinct stages: first forming the anti-stiction bumps, then creating the cavity. This segmentation allows independent optimization of bump dimensions and cavity geometry, resolving the contradiction between achieving adequate stiction reduction and maintaining precise dimensional control
2Reliability
If the size of anti-stiction bumps is reduced to minimize stiction, then stiction is reduced, but lithographic problems such as reduced processing window and photoresist collapse occur
Solution Approach 1:
By forming the anti-stiction bumps in advance before cavity formation, the patent enables the use of larger, more lithographically-friendly bump dimensions that are optimized for stiction reduction without being constrained by subsequent processing steps. This preliminary formation avoids the lithographic problems associated with attempting to form smaller features
3Ease of manufacture
If the sidewall angle of anti-stiction bumps is increased, then the bumps are easier to form, but stiction between substrate and MEMS device increases
Solution Approach 1:
The patent forms the anti-stiction bumps with optimized sidewall angles in advance, before cavity formation imposes geometric constraints. This allows selection of sidewall angles that minimize stiction while remaining manufacturable, resolving the contradiction between ease of formation and stiction reduction
Data Source
AI summary
The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.