MEMS Chip Embedding in Mold Compound for Compact Packaging

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Solution Overview

Problem

Current chip packaging technologies, such as wire bonding, result in large package footprints and heights, which are not suitable for future technology nodes that require smaller form factors and reliable electrical performance.

Innovation Solution

A chip arrangement involving a microelectromechanical systems (MEMS) device partially embedded in a mold compound, with an interconnect structure that includes through-vias and redistribution layers to reduce footprint and height, while ensuring reliable electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional wire bonding packaging is used, then electrical connections are established, but the package footprint and height become large

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpackage footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar wire bonding to three-dimensional vertical interconnections using through-vias and stacked chip architecture. Electrical connections are established in the vertical dimension rather than lateral dimension, enabling compact footprint while maintaining connection reliability through direct vertical pathways.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested stacking where multiple functional chips are vertically integrated within a compact package structure. Through-vias penetrate through upper chips to connect to lower chips, creating a nested arrangement that maximizes electrical connection density while minimizing package footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Reliability

If traditional wire bonding packaging is used, then electrical connections are established, but the package height increases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidpackage height

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent redistributes electrical connections from lateral wire bonds to vertical through-vias, compressing the package height by eliminating the need for lateral wire bond loops while maintaining electrical connection reliability through direct vertical pathways.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If chip embedding is used to reduce footprint, then lateral extent decreases, but manufacturing complexity increases

Engineering Contradiction:

Improvepackage footprintVSAvoidmanufacturing process complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent performs preliminary alignment and positioning of chips on the carrier before molding, ensuring precise through-via placement and electrical connections are established prior to the molding process. This preliminary action simplifies the overall manufacturing by preventing defects rather than requiring complex post-processing.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The manufacturing process is segmented into distinct stages: chip placement on carrier, through-via formation, molding compound application, and carrier removal. This segmentation allows each process step to be optimized independently, reducing overall manufacturing complexity despite the advanced three-dimensional architecture.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9856136B2Chip arrangement and method for manufacturing a chip arrangement

Publication Date: 2018.01.02 SONY GROUP CORP

AI summary

A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.