MEMS Gyroscope PLL Clamp for Stable Startup Frequency Control
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Solution Overview
Problem
The operational frequency range of the phase-locked loop (PLL) in MEMS gyroscopes is limited, as excessively broad frequencies can complicate timing closure in digital processing circuits and lead to erroneous locking into spurious modes, especially during power interruptions, compromising the gyroscope's startup and stability.
Innovation Solution
A phase-locked loop circuit with a programmable clamp is implemented to regulate the output frequency, using a programmable clamp circuit to generate a limited voltage control signal that calibrates the PLL output within the operating range of digital circuits, preventing excessive frequencies and ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the operational frequency range of the PLL is set broadly to account for manufacturing variations, then the PLL can accommodate process variations in MEMS and ASIC, but timing closure in digital processing circuits becomes complicated and the risk of locking into spurious modes increases
Solution Approach 1:
The frequency range is segmented into multiple discrete bands using banked dividers with different division ratios. Instead of using a single broad frequency range, the system divides the frequency spectrum into manageable segments, each handled by a specific divider configuration, thereby simplifying timing closure while maintaining adaptability across process variations
Solution Approach 2:
The system dynamically selects appropriate divider ratios based on the detected resonance frequency. The frequency-to-digital converter and control logic adjust the active divider configuration in real-time, allowing the PLL to adapt its frequency range dynamically rather than maintaining a fixed broad range, thus simplifying timing closure for each specific operating condition
2Reliability
If the PLL output frequency range is set broadly to ensure startup under varying conditions, then the gyroscope can start up across different manufacturing processes, but the risk of erroneous locking into spurious modes increases during power interruptions
Solution Approach 1:
A frequency-to-digital converter provides feedback about the detected resonance frequency to the control logic. This feedback mechanism enables the system to identify when the PLL is approaching spurious modes and adjust the divider ratio accordingly, preventing erroneous locking while maintaining broad startup capability through continuous monitoring and adjustment
Solution Approach 2:
The system preemptively adjusts the divider ratio based on the detected frequency before spurious mode locking can occur. By anticipating potential locking issues and modifying the frequency division in advance, the system prevents harmful spurious mode locking while maintaining the ability to start up reliably across varying conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The programmable clamp effectively limits the PLL output frequency, preventing digital circuit damage and ensuring robust startup and stable operation of the MEMS gyroscope, even under varying conditions and power interruptions.
Implementation Method 1
a voltage-controlled oscillator configured to receive the second analog control signal and generate an output signal having a regulated frequency
Data Source
AI summary
According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.