MEMS Package Wafer Cover with Integrated Metal Shielding
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Solution Overview
Problem
Conventional microelectromechanical system packages are difficult to mass-produce and have a large profile, limiting their application due to the need for additional protective covers and electromagnetic interference shielding.
Innovation Solution
A method using a wafer as a cover for microelectromechanical system chips, where the wafer is etched to form cavities and metal layers for shielding, reducing package thickness and eliminating the need for additional covers, with bonding wires connecting components for electrical shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional package structure with separate cover and shielding layers is used, then electromagnetic interference shielding is achieved, but the package thickness increases and mass production becomes difficult
Solution Approach 1:
The patent combines the cover structure and electromagnetic shielding function into a single integrated wafer component. The wafer includes both the protective cover structure and conductive shielding layers formed by depositing conductive material on the inner surface, eliminating the need for separate cover and shielding components while reducing overall package thickness.
Solution Approach 2:
The wafer serves multiple functions simultaneously: it provides mechanical protection as a cover, electromagnetic interference shielding through conductive layers, and structural support. This multi-functional design replaces what would traditionally require multiple separate components, enabling both shielding and thickness reduction goals to be achieved.
2Object-affected harmful factors
If a conventional package with additional cover and shielding components is used, then electromagnetic interference shielding is achieved, but device complexity increases
Solution Approach 1:
The patent merges the cover and shielding functions into a single wafer component with integrated conductive shielding layers. This consolidation reduces the number of discrete parts and assembly steps, thereby simplifying the overall package structure while maintaining effective electromagnetic interference shielding.
Solution Approach 2:
The patent changes the structural parameters of the wafer by forming conductive shielding layers on its inner surface through deposition processes. This parameter modification enables the wafer to provide both mechanical protection and electromagnetic shielding in a unified structure, reducing complexity compared to conventional multi-component designs.
3Object-affected harmful factors
If conventional packaging methods are used, then electromagnetic interference shielding is achieved, but manufacturing efficiency decreases
Solution Approach 1:
The patent segments the wafer into multiple units with individual cavities using scribe streets, allowing parallel processing and batch manufacturing. This segmentation enables efficient mass production where multiple MEMS devices can be fabricated and packaged simultaneously on the same wafer substrate, significantly improving manufacturing efficiency.
Solution Approach 2:
The patent performs preliminary actions by forming the complete wafer structure with integrated shielding layers before dicing into individual devices. The conductive shielding layers are deposited on the wafer's inner surface prior to segmentation, allowing shielding functionality to be established early in the manufacturing process rather than requiring subsequent assembly steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces package thickness and enhances performance by using the wafer cover for electromagnetic interference shielding, allowing for more efficient and compact microelectromechanical system packages.
Implementation Method 1
The lower surface of the first wafer is bonded to a second wafer with a plurality of microelectromechanical system chips
Data Source
AI summary
A microelectromechanical system package includes a chip carrier, a first microelectromechanical system chip, a silicon cover, a layer of metal, a plurality of first bonding wires and a sealant. The first microelectromechanical system chip is positioned on the chip carrier and has an active surface, and an active area on the active surface. The layer of metal is formed on the upper surface of the cover. The first bonding wires electrically connect the active surface of the first microelectromechanical system chip to the chip carrier. The sealant is formed on the chip carrier to encapsulate the first microelectromechanical system chip and the first bonding wires.