MEMS Wafer Stack Insulated Conducting Channels
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Solution Overview
Problem
Current methods for wafer-level integration of MEMS and IC devices face inefficiencies due to the need for additional processing steps, cost, and limited design flexibility, particularly with the use of Through-Silicon Vias (TSVs) which restrict device size and performance, and require external packaging and wire bonding.
Innovation Solution
A method involving a MEMS wafer stack with insulated conducting channels and a top cap wafer, bonded to an IC wafer, allowing for hermetic sealing and electrical pathways without TSVs, enabling direct solder-bonding to a PCB without additional packaging or wire bonding, thus eliminating the need for IC wafer thinning and additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon Vias (TSVs) are used for electrical connection, then electrical connectivity between MEMS and IC is achieved, but device vertical dimensions are restricted and design flexibility is limited
Solution Approach 1:
The patent transitions from vertical through-silicon via connections to a lateral routing approach where electrical connections are made through the wafer plane rather than through the thickness. The MEMS wafer is bonded to the IC wafer with bond pads aligned laterally, eliminating the need for vertical TSV penetrations and enabling greater design flexibility in vertical dimensions.
Solution Approach 2:
The invention extracts and eliminates the TSV structure from the integration process. By removing the requirement for through-silicon vias, the patent simplifies the manufacturing process and removes the dimensional constraints that TSVs impose on device design and performance.
2Reliability
If IC wafer is thinned to accommodate TSVs, then electrical pathways through silicon are enabled, but additional processing steps and manufacturing complexity increase
Solution Approach 1:
Instead of thinning the IC wafer to create TSV pathways, the patent inverts the approach by maintaining full wafer thickness and creating electrical connections through lateral bonding interfaces. This eliminates the need for wafer thinning and the associated complex processing steps while still achieving reliable electrical pathways.
3Reliability
If wire bonding and external packaging are used, then electrical connections are established, but manufacturing cost and device size increase
Solution Approach 1:
The patent merges the electrical connection function directly into the wafer-level bonding process. By aligning and bonding bond pads laterally at the wafer level, the invention combines mechanical support and electrical connectivity into a single integration step, eliminating the need for separate wire bonding and external packaging operations.
4Adaptability or versatility
If MEMS and IC wafers are bonded directly, then integration is achieved, but IC layout efficiency decreases due to MEMS layout modifications
Solution Approach 1:
The patent applies partial action by modifying only the specific regions of the IC wafer where bond pad alignment is required, rather than requiring comprehensive layout modifications. This selective approach maintains overall IC layout efficiency while enabling wafer-level integration with MEMS devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for cost-effective, area-efficient, and flexible integration of MEMS and IC devices, enabling hermetic sealing and direct routing of electrical signals, reducing manufacturing complexity and increasing design flexibility while eliminating the need for wire bonding and external packaging.
Implementation Method 1
bonding the inner side of the MEMS wafer stack to the inner side of the integrated circuit wafer
Data Source
AI summary
A MEMS and a method of manufacturing MEMS components are provided. The method includes providing a MEMS wafer stack including a top cap wafer, a MEMS wafer and optionally a bottom cap wafer. The MEMS wafer has MEMS structures patterned therein. The MEMS wafer and the cap wafers include insulated conducting channels forming insulated conducting pathways extending within the wafer stack. The wafer stack is bonded to an integrated circuit wafer having electrical contacts on its top side, such that the insulated conducting pathways extend from the integrated circuit wafer to the outer side of the top cap wafer. Electrical contacts on the outer side of the top cap wafer are formed and are electrically connected to the respective insulated conducting channels of the top cap wafer. The MEMS wafer stack and the integrated circuit wafer are then diced into components having respective sealed chambers and MEMS structures housed therein.