Automatic Verification of Merged Mode Timing Constraints

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Solution Overview

Problem

The complexity of electronic circuit designs and the need for repeated timing analysis across various modes and corners result in high computational costs and error-prone manual merging of modes, making it difficult to verify the correctness of merged constraints in timing analysis.

Innovation Solution

A computer-implemented method for automatically verifying the equivalence of merged modes with respect to individual modes by identifying source and sink sets of timing nodes, traversing timing relationships, and comparing aggregate sets to detect errors in merged constraints, thereby ensuring correctness and reducing manual errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If manual merging of modes is performed, then device complexity is reduced, but reliability deteriorates due to error-prone manual verification

Engineering Contradiction:
Improvemode merging complexityVSAvoidmerged mode correctness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system performs automatic self-verification of merged modes by comparing timing relationships against original individual modes, eliminating the need for manual verification and reducing errors while maintaining complexity reduction

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The verification process provides feedback by identifying and reporting timing relationships that exist in merged modes but not in individual modes, allowing automatic correction or validation of the merging process

Inventive Principle:
Principle #23Feedback

2Reliability

If timing analysis is performed for all mode and corner combinations, then reliability is improved, but productivity deteriorates due to excessive computational time

Engineering Contradiction:
Improvetiming verification completenessVSAvoiddesign iteration speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary verification by checking timing relationships before final sign-off, allowing merged modes to be used during implementation phase without compromising final reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs partial verification by focusing on identifying extraneous timing relationships rather than complete re-verification of all timing paths, reducing computational overhead while maintaining reliability

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If merged modes are used for sign-off, then productivity is improved, but reliability deteriorates without automatic verification

Engineering Contradiction:
Improvedesign closure speedVSAvoidmerged mode accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The merged modes perform self-verification by automatically comparing their timing relationships against the original individual modes, enabling confident use for sign-off without manual intervention

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system replaces manual verification processes with automated computer-based verification, substituting human effort with algorithmic comparison of timing relationships

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8607186B2Automatic verification of merged mode constraints for electronic circuits
Publication Date: 2013.12.10 SYNOPSYS INC
  • US8607186B2 patent drawing
  • US8607186B2 patent drawing
  • US8607186B2 patent drawing

AI summary

Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.