Metadata-Buffer Accelerator Control for Low-Overhead Real-Time Processing

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Solution Overview

Problem

Conventional accelerator technologies face challenges in increasing the speed of real-time processing due to overheads such as memory copies and interrupt notifications, especially when multiple accelerators are involved, leading to reduced scalability.

Innovation Solution

An accelerator control system that includes an accelerator control device and an accelerator, where the device stores control data including the location and processing content, and the accelerator autonomously performs arithmetic processing and notifies completion through metadata buffers, reducing overheads and enabling asynchronous operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If accelerators are controlled by the CPU with interrupt notifications for each processing step, then the CPU can manage accelerator operations, but processing overhead increases and real-time processing speed decreases

Engineering Contradiction:
ImproveCPU control of acceleratorVSAvoidreal-time processing speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The accelerator autonomously manages its own operations by reading control data from metadata buffers and writing results without requiring continuous CPU intervention or interrupt notifications for each processing step, thereby reducing overhead while maintaining operational capability

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

Control data including processing instructions and data locations is prepared in advance in metadata buffers, allowing the accelerator to execute operations autonomously without waiting for real-time CPU commands or interrupt signals

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If memory copies occur between user space and kernel space for data reading and writing, then data transfer is enabled, but processing overhead increases and delay time increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidprocessing delay time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

Metadata buffers serve as an intermediary structure that stores control data and enables the accelerator to access processing information without requiring frequent memory copies between user space and kernel space, reducing transfer overhead and delay

Inventive Principle:
Principle #24Intermediary (Mediator)

3Power

If multiple accelerators are deployed to increase processing capability, then computational power increases, but overhead for each accelerator increases and scalability is reduced

Engineering Contradiction:
Improvecomputational powerVSAvoidsystem scalability
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The metadata buffer structure provides a universal control mechanism that can manage multiple accelerators uniformly, with each accelerator accessing control data through the same buffer interface, thereby enabling scalable deployment without increasing per-accelator overhead

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12417097B2Accelerator control system, accelerator control method and accelerator control program
Publication Date: 2025.09.16 NT T INC
  • US12417097B2 patent drawing
  • US12417097B2 patent drawing
  • US12417097B2 patent drawing

AI summary

An accelerator control system includes an accelerator control device and an accelerator, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and the accelerator includes second processing circuitry configured to acquire the control data from the storage, perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying content of arithmetic processing of the accelerator included in the acquired control data, and store the control data in the storage when the arithmetic processing is completed.