Metadata-Driven FPGA Counter Parsing in Network Devices
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Solution Overview
Problem
Existing network device parsers for FPGA counter data records require time-consuming updates when new counter types are introduced, as they are hard-coded for specific counter data record types, making them inefficient for re-programmable FPGAs.
Innovation Solution
A metadata-driven framework that generates a counter descriptor file during FPGA image creation, allowing for generic parsing logic by using registry entries to define counter data record types, enabling efficient parsing without requiring frequent updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hard-coded parsing logic is used for specific counter data record types, then parsing accuracy for known counter types is maintained, but parser updates become time-consuming when new counter types are introduced
Solution Approach 1:
The system performs preliminary action by generating and storing a counter descriptor file during FPGA image creation, which contains definitions of all counter data record types. This pre-prepared metadata enables the parser to immediately understand new counter types without requiring updates to the parser itself, thus resolving the contradiction between adaptability and update time.
Solution Approach 2:
The counter descriptor file acts as an intermediary between the FPGA application image and the parser. Instead of modifying the parser to handle new counter types, the descriptor file provides the parser with the necessary information about counter data record structures, eliminating the need for parser updates while maintaining full adaptability.
2Productivity
If hard-coded parsing logic is used for specific counter data record types, then parser implementation is straightforward, but the parser cannot efficiently handle re-programmable FPGA counter types
Solution Approach 1:
The counter descriptor file serves as an intermediary that contains all the complexity of counter type definitions. The parser itself remains simple and generic, merely reading the descriptor file and using the provided information to parse counter data records. This separates the complexity from the parser, improving parsing efficiency while managing device complexity.
Solution Approach 2:
All complex counter type definitions are prepared in advance in the counter descriptor file during FPGA image creation. The parser only needs to perform simple lookups and parsing operations based on this pre-prepared information, significantly improving parsing efficiency without requiring a complex parser implementation.
Data Source
AI summary
Techniques for parsing FPGA counter data records in a network device with an FPGA are provided. In one set of embodiments these techniques include ingesting, by the network device, a metadata file associated with an application image programmed in (or configured to be programmed in) the FPGA, where the metadata file includes definitions of counter data record types that are used (i.e., reported via counter messages) by the application image. The techniques further include receiving a counter message from the FPGA that includes one or more counter data records and, for each record, retrieving the ingested definition of that record's type and parsing the record in accordance with the definition.