Metal Gate Structure with Protective Capping Layer
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing metal gate structures for nanometer technology process nodes, particularly in achieving reliable gate electrodes and durable metal layers that withstand etching processes without damage, especially when using high-k dielectric materials and three-dimensional designs like Fin FETs.
Innovation Solution
A method involving the formation of dummy gate structures, followed by the sequential deposition and recessing of metal layers with specific work function adjustment layers and insulating layers, ensuring durability against etching gases like Cl and F, and using a dual damascene process for via plug formation to prevent damage to metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal gate structures are manufactured using gate replacement technologies for nanometer process nodes, then device density and performance are improved, but the metal layers become vulnerable to damage from etching processes
Solution Approach 1:
A protective capping layer is formed over the metal gate structure before subsequent processing steps. This preliminary protective action prevents damage to the metal layers during etching processes, solving the vulnerability issue while maintaining the benefits of gate replacement technologies for high device density
Solution Approach 2:
An intermediary protective layer is introduced between the etching process and the metal gate structure. This intermediary layer acts as a buffer that protects the metal layers from direct exposure to harmful etching gases, thereby maintaining reliability during high-density manufacturing
2Reliability
If high-k dielectric materials are used in metal gate structures, then device performance is improved, but the structure becomes more sensitive to etching damage
Solution Approach 1:
The protective capping layer transforms the harmful effect of etching gases into a controlled process. The layer is designed to be selectively removable after serving its protective function, converting the potential harm of exposure to etching gases into a beneficial protective mechanism that can be precisely controlled and removed when no longer needed
3Reliability
If multiple metal layers are deposited for gate replacement, then gate electrode quality is improved, but the complexity of preventing erosion during processing increases
Solution Approach 1:
Multiple protective functions are merged into a single integrated capping layer structure. This unified approach provides simultaneous protection for all metal layers during processing, reducing the overall processing complexity compared to treating each metal layer separately while maintaining high gate electrode quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of robust metal gate structures that withstand etching processes, maintaining the integrity of metal layers and preventing erosion, thus enhancing the manufacturing efficiency and reliability of semiconductor devices.
Implementation Method 1
A first metal layer is formed over the gate dielectric layer and the fin structure
Implementation Method 2
A second metal layer is formed over the first metal layer in the gate recess
Implementation Method 3
A gate recess is formed by removing an upper portion of the filled first metal layer
Data Source
AI summary
A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.