Metal Gate Contact via Selective Etch Liner
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Solution Overview
Problem
Conventional polysilicon gates face challenges with high-κ dielectrics due to transistor threshold voltage pinning and dopant penetration issues, leading to high resistance and complexity in forming low resistance connections in MOSFETs, especially as transistors are scaled to smaller sizes.
Innovation Solution
A method involving a high-κ gate dielectric and metal gate stack with a liner layer and fill material is used, where a layer of fill material is deposited and etched to form low resistance connections, allowing for metal filling through the openings, decoupling contact resistance from gate stack geometry and enabling planarization for fine pitch connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gates are used with high-κ dielectrics, then the gate structure can be formed, but transistor threshold voltage pinning occurs and dopant penetration issues arise
Solution Approach 1:
The patent extracts and removes the problematic polysilicon gate material from the high-κ dielectric interface. By replacing polysilicon with metal gate materials (such as titanium nitride, tungsten, or other metals), the Fermi level pinning effect and dopant penetration issues are eliminated while maintaining effective gate control over the transistor channel.
Solution Approach 2:
The patent changes the material parameter of the gate electrode from polysilicon to metal or metal alloy. This material substitution fundamentally alters the electrical properties at the gate-dielectric interface, eliminating threshold voltage pinning while providing better control over the electric field in the channel.
2Reliability
If polysilicon is doped to reduce gate resistance, then gate resistance decreases, but dopant penetration into the transistor channel area becomes problematic
Solution Approach 1:
The patent removes the need for doping by extracting the dopant requirement entirely. Metal gate materials inherently provide low resistance without requiring dopant introduction, thereby eliminating the harmful effect of dopant penetration into the transistor channel while maintaining low gate resistance.
Solution Approach 2:
The patent uses metal gate materials that provide low resistance intrinsically without requiring additional doping steps. This replaces the complex doping process with a simpler material selection approach, where the metal gate's natural conductivity suffices.
3Manufacturing precision
If sidewalls are formed by isotropic deposition followed by anisotropic etch to control impurity implantation, then implantation location is controlled, but substantial gate stack height is required to achieve desired sidewall thickness
Solution Approach 1:
The patent changes the material composition of the gate stack to metal-based materials that enable thinner gate stacks while maintaining structural integrity. This allows sidewalls to be formed with adequate thickness using the same isotropic deposition and anisotropic etch process, reducing the overall gate stack height requirement while preserving implantation location control.
4Manufacturing precision
If fill material is deposited to overfill spaces between transistor gate and other structures for planarization, then accurate formation of fine conductors is supported, but the resistance within the gate stack becomes higher than desired
Solution Approach 1:
The patent changes the gate electrode material to metal with inherently lower resistance than polysilicon. This material substitution reduces the gate stack resistance to acceptable levels while maintaining the planarization approach with fill material deposition, thereby supporting accurate formation of fine conductors without the resistance penalty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in low resistance contacts to the transistor gate and source/drain regions, enhancing integration density and manufacturing yield by simplifying the etching process and reducing dopant-related complications, while allowing for flexible material choices and improved carrier mobility.
Implementation Method 1
The transistor threshold voltage is usually determined or modulated by metal gate work function
Implementation Method 2
high-κ gate insulators improve control of the electric field in the transistor channel
Implementation Method 3
forming silicided regions corresponding to at least one of a source and a drain of said transistor
Implementation Method 4
selectively etching the fill material to the liner layer; selectively etching the liner layer and the gate stack to the metal gate
Data Source
AI summary
A low resistance contact is formed to a metal gate or a transistor including a High-κ gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.