Metal Gate Work Function Tuning via Dopant Diffusion
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Solution Overview
Problem
The integration of metal gates with high-K dielectric layers in semiconductor devices, particularly in CMOS technology, faces challenges such as thermal stability and achieving appropriate threshold voltages due to the Fermi-Pinning Effect, leading to complex manufacturing processes and high costs for mass production.
Innovation Solution
A method that adjusts the effective work functions of MOSFETs by implanting dopant ions into the metal gate layer, allowing dopant ions to diffuse and form electric dipoles at specific interfaces, thereby simplifying the process and enabling mass production by eliminating the need for multiple metal gate and dielectric combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different combinations of metal gate and high-K dielectric layer are used for NMOSFET and PMOSFET to achieve appropriate threshold voltages, then the threshold voltage requirement is satisfied, but the manufacturing process becomes complicated and cost increases
Solution Approach 1:
The patent applies local quality by implanting different dopant types (N-type for NMOSFET, P-type for PMOSFET) into the metal gate layer of different device regions. This creates locally differentiated electrical characteristics while maintaining a unified global structure, allowing each transistor type to achieve its required threshold voltage without requiring different metal gate/dielectric combinations across the chip.
2Length of stationary object
If conventional Poly-Si gate is used with high-K gate dielectric layer, then the physical thickness can be increased, but the exhaustion effect occurs and gate resistance increases
Solution Approach 1:
The patent changes the material parameter of the gate from conventional Poly-Si to metal gate layer, which fundamentally alters the electrical characteristics. The metal gate eliminates the exhaustion effect inherent in Poly-Si when used with high-K dielectrics, while also reducing gate resistance. This parameter change allows the high-K dielectric layer to achieve its full potential in providing increased physical thickness for better gate control.
3Reliability
If metal gate and high-K dielectric layer are integrated, then gate resistance decreases and boron penetration is avoided, but thermal stability and interface state problems occur
Solution Approach 1:
The patent applies preliminary action by performing dopant ion implantation into the metal gate layer before the high-temperature activation annealing process. This pre-positioning of dopants allows them to diffuse to appropriate locations during the subsequent annealing process, establishing the desired electrical characteristics before final device formation. This sequencing helps manage thermal effects while achieving the required doping profiles.
4Device complexity
If dopant ions are implanted in the metal gate layer to adjust effective work function, then the manufacturing process is simplified, but additional implantation steps are required
Solution Approach 1:
The patent merges the threshold voltage adjustment function into the existing metal gate layer formation process by incorporating dopant ion implantation. Instead of requiring separate processes for different metal gate/dielectric combinations, the dopant implantation is integrated into the gate fabrication sequence, allowing threshold voltage control to be achieved through a unified process that combines gate formation and doping steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the adjustment of threshold voltages in CMOS devices by changing dopants, simplifying the manufacturing process, and improving the stability and effectiveness of the semiconductor device by adjusting the effective work function of the metal gate.
Implementation Method 1
during activation annealing for forming the S/D regions, the dopant ions in the metal gate layer diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the metal gate layer and at a lower interface between the high-K gate dielectric layer and the interfacial oxide layer
Implementation Method 2
electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interfacial oxide layer
Implementation Method 3
implanting dopant ions in the metal gate layer, that is an N-type dopant is implanted into the metal gate layer of the active region of the N-type MOSFET, and a P-type dopant is implanted into the metal gate layer of the active region of the P-type MOSFET
Data Source
AI summary
A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.