Metal Gate Etch Selectivity Control in Semiconductor Manufacturing
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Solution Overview
Problem
The multi patterning gate (MPG) process loop in semiconductor manufacturing often damages metal gate electrodes, leading to undesirable reduction in gate height, which affects device performance.
Innovation Solution
A method is introduced that involves forming a first and second layer of conductive material in gate spaces, using a conductive material like tungsten as a hard mask to control etch selectivity, reducing gate height loss by adjusting etching processes, and employing a planarization process to form short and long channel gates with minimized height reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional MPG loop process is used, then gate patterning is achieved, but gate height is significantly reduced (up to 10 nm loss)
Solution Approach 1:
The patent changes the etch selectivity parameters by using a conductive material (tungsten) as hard mask that has different etch resistance properties compared to traditional masks. This allows control over the etching rate differential between the gate metal and the hard mask layer, thereby reducing gate height loss during the MPG loop process
Solution Approach 2:
The conductive material layer serves as an intermediary hard mask between the patterning process and the gate metal. This intermediary layer protects the gate metal from excessive etching while still allowing precise patterning to occur, thus maintaining gate height integrity
2Length of moving object
If etch selectivity is increased to protect gate height, then gate height loss is reduced, but etching process complexity increases
Solution Approach 1:
The patent merges the gate metal material (conductive material like tungsten) with the hard mask function. By using the same conductive material for both the gate electrode and the hard mask layer, the process eliminates the need for separate mask materials and simplifies the overall etching process while maintaining gate height protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate height loss, improving device performance by maintaining gate height integrity during the MPG loop, with gate height loading reduced to less than 3 nm compared to traditional methods which experience losses of up to 10 nm.
Implementation Method 1
A first etching operation is performed to remove the hard mask layer and a top portion of the conductive material in the gate space for the short channel gate
Implementation Method 2
A planarization process is performed, thereby forming the short channel gate and the long channel gate
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. A first portion of the top layer is removed to leave a hard mask layer over a long channel gate region. The hard mask layer and a portion of heights of the conductive material in the gate spaces are removed to form a first structure. A second layer of the conductive material is formed over the first structure. Portions of the second layer are removed to create a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate.