Metal Gate Insulating Plugs for CMP Dishing Prevention
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Solution Overview
Problem
In the manufacturing of high voltage metal-oxide-semiconductor transistors, the process of chemical mechanical polishing (CMP) often results in gate dishing due to the large size of the metal gates, which affects the transistor's performance and yield.
Innovation Solution
Incorporating insulating plugs within the metal gate structure to serve as a stop layer during the CMP process, preventing over-polishing and thus reducing gate dishing, while maintaining the electrical performance of the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the metal gate size is increased to accommodate high voltage operation requirements, then the transistor can withstand higher voltages, but gate dishing occurs during CMP process
Solution Approach 1:
The gate structure is segmented by introducing insulating plugs that divide the continuous metal gate into multiple sections. This segmentation allows the CMP process to remove material uniformly without causing dishing across the entire gate area, while still maintaining the required voltage blocking capability through the combined effect of multiple segmented regions.
Solution Approach 2:
Insulating plugs are introduced as intermediary elements within the gate structure. These plugs serve as mediators that prevent direct CMP contact with the underlying metal gate material in certain regions, thereby preventing over-polishing and dishing while allowing the metal gate to maintain its voltage blocking function in the remaining areas.
2Reliability
If the metal gate dimensions are increased for high voltage applications, then voltage endurance is improved, but CMP process control becomes difficult
Solution Approach 1:
The large metal gate area is divided into multiple smaller effective regions by insulating plugs. This segmentation enables better CMP process control by limiting the continuous metal area that undergoes polishing, reducing the likelihood of dishing while maintaining overall voltage endurance through the collective effect of all gate segments.
Solution Approach 2:
Insulating plugs are pre-positioned within the gate structure before the CMP process. This preliminary action creates predetermined protection zones that guide the CMP process, ensuring uniform material removal and preventing dishing before it can occur during the actual polishing operation.
3Manufacturing precision
If insulating plugs are added to prevent gate dishing, then manufacturing precision is improved, but device structure becomes more complex
Solution Approach 1:
The insulating plugs serve multiple functions simultaneously: they act as CMP stop layers to prevent dishing, serve as structural elements to define gate regions, and provide electrical isolation within the gate. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity.
Solution Approach 2:
The insulating plugs are integrated into the existing gate fabrication process flow, combining the dishing prevention function with the standard gate formation steps. By merging the protective function into the existing structure rather than adding separate protective layers, the increase in device complexity is minimized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of insulating plugs effectively prevents gate dishing and enhances the manufacturing yield by acting as a stop layer during CMP, improving the gate structure and performance of high voltage metal-oxide-semiconductor transistors.
Implementation Method 1
the process of chemical mechanical polishing (CMP) often results in gate dishing due to the large size of the metal gates
Data Source
AI summary
A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.