Metal Gate Structures for Semiconductor Devices
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Solution Overview
Problem
Existing 'gate last' processes for forming metal gates in semiconductor devices are not entirely satisfactory as device scaling-down continues, particularly due to challenges in aligning contacts with narrow metal gate structures and preventing shorts, which can lead to damage and threshold voltage changes.
Innovation Solution
The solution involves forming wide and narrow metal gate structures with a sealing layer and spacers, followed by a contact etch stop layer, and using an etching back process with a mask to protect the wide metal gate while shortening the narrow metal gate, and then forming an insulating layer to prevent shorts and ensure self-aligned contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration levels, then productivity and integration density are improved, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The patent applies preliminary action by forming a contact etch stop layer and sealing layer on the narrow metal gate structure before performing the etching back process. This preparatory step ensures that the narrow gate is protected and properly defined before the shortening operation, preventing alignment issues and shorts that would otherwise occur during the etching process.
Solution Approach 2:
The patent introduces intermediary layers (contact etch stop layer and sealing layer) between the etching process and the narrow metal gate structure. These intermediary layers act as protective mediators that prevent direct exposure of the narrow gate to the etching process, thereby maintaining manufacturing precision while enabling the productivity benefits of device scaling.
2Manufacturing precision
If etching back process is used to shorten narrow metal gate, then contact alignment is improved, but wide metal gate may be damaged and threshold voltage changes
Solution Approach 1:
The patent applies local quality by selectively protecting only the narrow metal gate structure with the contact etch stop layer and sealing layer, while leaving the wide metal gate exposed. This localized protection approach allows the etching back process to shorten the narrow gate for improved contact alignment without affecting the wide gate's dimensions or electrical characteristics, thereby maintaining threshold voltage stability.
Solution Approach 2:
The patent segments the metal gate structures into wide and narrow portions with different protective treatments. The narrow gate receives specialized protection through the contact etch stop layer and sealing layer, while the wide gate remains unprotected during etching back. This segmentation enables differential processing that achieves contact alignment for narrow gates while preserving the electrical integrity of wide gates.
3Productivity
If contacts are formed adjacent to narrow metal gate structures, then device integration is improved, but shorts between contacts and gates increase
Solution Approach 1:
The patent applies beforehand cushioning by depositing the contact etch stop layer and sealing layer on the narrow metal gate structure prior to the etching back process. These layers create a protective cushion that prevents the etching process from creating shorts between the contact and the narrow gate, while still allowing the gate to be shortened for better alignment. This preventive measure eliminates the harmful shorts that would otherwise occur in highly integrated devices.
Data Source
AI summary
Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.