High-k Metal Gate Tungsten Cap for Lower Contact Resistance
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Solution Overview
Problem
The increasing demand for higher storage capacity, faster processing, and lower costs in semiconductor devices has led to the complexity of manufacturing processes, particularly in scaling down metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (FinFETs).
Innovation Solution
The fabrication method involves forming multi-gate devices with a gate structure on multiple sides of the channel region, using a gate-last process to replace a dummy gate with a high-K/metal gate stack, and incorporating a tungsten cap as an intermediary between the metal gate and conductive plug to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to increase storage capacity and processing speed, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The gate structure is segmented into multiple distinct layers including high-k dielectric layer, metal gate layer, and tungsten cap layer. This segmentation allows each layer to be optimized independently for its specific function while managing the complexity of scaled-down device manufacturing
Solution Approach 2:
A dummy gate structure is formed preliminarily during FinFET fabrication, which is later replaced with the high-k/metal gate stack with tungsten cap. This preliminary action allows the gate-last process to be implemented without disrupting the existing FinFET manufacturing flow, thereby improving processing speed without proportionally increasing manufacturing complexity
2Speed
If a high-K/metal gate stack is used to improve device performance, then switching speed is improved, but contact resistance increases
Solution Approach 1:
A tungsten cap layer is introduced as an intermediary between the metal gate and the conductive plug. This tungsten cap serves as a mediator that provides excellent contact properties, reducing contact resistance while allowing the high-k/metal gate stack to maintain its high switching speed performance
Solution Approach 2:
The gate structure uses a composite material approach by combining high-k dielectric material, metal gate material, and tungsten cap material. Each material is selected for its specific properties, and their combination creates a structure that simultaneously achieves low contact resistance and high switching speed
3Reliability
If continuous tungsten cap is formed over the gate structure, then contact resistance is reduced, but manufacturing process steps increase
Solution Approach 1:
The tungsten cap is formed as part of the gate-last process, which is integrated into the existing FinFET manufacturing flow. By performing the tungsten cap formation preliminarily during the gate structure fabrication, additional process steps are minimized while still achieving reduced contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing resistance and improving the manufacturing process efficiency, aligning with the demands for higher capacity and faster processing.
Implementation Method 1
incorporating a tungsten cap as an intermediary between the metal gate and conductive plug to reduce resistance
Data Source
AI summary
Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.