Metal Layer Thickness Control in Semiconductor Packaging
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Solution Overview
Problem
The increasing complexity and demand for high-frequency applications in semiconductor devices pose challenges in reducing signal channel lengths, improving heat dissipation, internal ohmic resistance, robustness, and manufacturing costs, particularly in silicon chip packaging.
Innovation Solution
A method involving the application of a metal ions containing solution to create a first metal layer of a specific thickness and a second metal layer of a different thickness, with the latter being laterally spaced apart from the former, on an insulating layer over a carrier and chip, to enhance electrical connections while minimizing space and material usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional packaging methods are used for silicon chips, then manufacturing simplicity is maintained, but signal channel lengths cannot be sufficiently reduced and heat dissipation is poor
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, placing chips vertically on carrier substrates and using through-substrate vias to establish electrical connections. This dimensional change enables shorter signal paths while accommodating multiple functional layers within a compact footprint, directly resolving the contradiction between reduced signal channel length and packaging complexity.
Solution Approach 2:
The patent implements nested packaging by embedding chips within layered structures comprising carrier substrates, insulating layers, and conductive interconnects. Multiple functional elements are nested within each other vertically, allowing dense integration of power chips, logic chips, and passive components while maintaining short interconnect lengths through the stacked architecture.
2Temperature
If conventional packaging is used, then manufacturing cost is controlled, but heat dissipation performance is insufficient
Solution Approach 1:
The patent introduces carrier substrates as intermediary thermal management components between chips and the external environment. These substrates incorporate thermal vias and heat dissipation structures that conduct heat away from high-power chips, acting as thermal intermediaries that improve heat dissipation without requiring direct chip-to-heat-sink contact, thus managing thermal complexity separately from electrical packaging complexity.
3Reliability
If thicker metal layers are used throughout, then electrical resistance is reduced, but material usage and space consumption increase
Solution Approach 1:
The patent applies different metal layer thicknesses to different functional regions: thicker conductive layers are used in high-current power delivery paths and via structures, while thinner layers suffice for low-current signal interconnects. This localized differentiation optimizes electrical performance where needed while minimizing material consumption in less demanding regions, directly resolving the contradiction between connection quality and material usage.
4Speed
If signal channel lengths are reduced for high frequency applications, then performance is improved, but packaging space allocation becomes more difficult
Solution Approach 1:
The patent resolves the space-speed contradiction by moving electrical interconnects from lateral plane to vertical dimension through stacked packaging with through-substrate vias. This enables extremely short signal paths between chips while maintaining large lateral packaging area for I/O connections, allowing high-frequency performance without sacrificing packaging space for external connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient electrical connections with reduced resistance and space usage, enabling high-voltage, high-current, and complex logic applications on semiconductor devices, while maintaining cost-effectiveness and improved thermal management.
Implementation Method 1
applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer
Data Source
AI summary
This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.