Metal Line Layout for Reliable 3D MBCFET Logic Cells
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in achieving superior performance and integration while preventing stacking faults and maintaining channel resistance.
Innovation Solution
The semiconductor device incorporates a three-dimensional field effect transistor (MBCFET) design with vertically stacked semiconductor patterns, epitaxial source/drain patterns, and a gate dielectric layer that includes ferroelectric and paraelectric materials to enhance capacitance and reduce sub-threshold swing, along with an elongation etching process for forming metal layers to improve reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar MOSFET structures to three-dimensional vertically stacked channel structures. This dimensional change allows multiple channels to be stacked vertically, increasing device density without further lateral scaling, while maintaining acceptable operating characteristics through the vertical architecture that provides better gate control and reduced short-channel effects.
Solution Approach 2:
The patent implements vertically stacked channel structures where multiple channels are nested one above another in the vertical dimension. This nesting approach allows multiple functional channels to occupy a small footprint area, effectively increasing integration density while each channel maintains its operational integrity and characteristics.
2Ease of manufacture
If conventional planar structures are used, then manufacturing is simpler, but stacking faults occur and channel resistance increases
Solution Approach 1:
By moving to vertical stacking, the patent achieves better control over channel formation and reduces stacking faults. The vertical architecture allows for epitaxial growth methods that provide atomic-level precision in forming the channel stacks, overcoming the limitations of planar approaches where stacking faults and resistance control become difficult.
3Ease of manufacture
If standard dielectric layers are used, then manufacturing is easier, but capacitance is insufficient and sub-threshold swing is high
Solution Approach 1:
The patent employs composite dielectric structures including high-k dielectric materials combined with ferroelectric layers. This composite approach provides enhanced capacitance due to the high-k material's superior dielectric constant, while the ferroelectric component enables sub-60mV/decade sub-threshold swing through its negative capacitance effect, overcoming the limitations of standard dielectric layers.
Solution Approach 2:
The patent changes the dielectric parameter by introducing high-k and ferroelectric materials with fundamentally different electrical properties compared to standard dielectrics. This parameter change enables achieving low sub-threshold swing and high capacitance, which are critical for ultra-low power device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the operating characteristics of MOSFETs by reducing stacking faults, enhancing channel resistance, and achieving sub-threshold swing of less than 60 mV/decade, while increasing the reliability and yield of semiconductor devices through precise control of metal layer formation.
Implementation Method 1
a gate dielectric layer between the channel pattern and the gate electrode
Implementation Method 2
which includes ferroelectric and paraelectric materials to enhance capacitance
Implementation Method 3
which includes ferroelectric and paraelectric materials to enhance capacitance
Implementation Method 4
along with an elongation etching process for forming metal layers to improve reliability and yield
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a logic cell on a substrate, and a first metal layer on the logic cell. The first metal layer includes first and second power lines and first to third lower lines on first to third wiring tracks therebetween. The first to third wiring tracks extend in parallel in the first direction. The first lower line includes first and second lines spaced apart in the first direction from each other at a first distance. The third lower line includes third and fourth lines spaced apart in the first direction at a second distance. The first line has a first end facing the second line. The third line has a second end facing the fourth line. A curvature at the first end is substantially the same as that at the second end.