Metal Oxide Shift Register Circuit for Stable Display Scanning
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Solution Overview
Problem
Existing gate drive circuits in display devices, particularly those using low-temperature polycrystalline thin film transistors, face complexity in manufacturing, difficulty in achieving large sizes, and limitations in performance and output signal quality.
Innovation Solution
A shift register unit comprising an input circuit, control circuits, output circuit, discharge circuit, and node voltage limitation circuit, implemented with metal oxide thin film transistors, to provide stable and efficient scanning signals for display devices, utilizing transistors with specific configurations and capacitors to enhance signal control and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If low-temperature polycrystalline thin film transistors are used to enhance brightness and reduce power consumption, then display performance is improved, but manufacturing process complexity increases and large-sized device fabrication becomes difficult
Solution Approach 1:
The patent changes the material parameter from low-temperature polycrystalline silicon to metal oxide semiconductor, fundamentally altering the transistor characteristics. This material substitution eliminates the need for laser crystallization and ion implantation processes, thereby reducing manufacturing complexity while maintaining or improving display performance including brightness and power consumption
Solution Approach 2:
The patent employs a simpler manufacturing process using metal oxide thin film transistors that can be fabricated with standard semiconductor processing techniques, replacing the complex and expensive laser crystallization process. This approach enables cost-effective production of large-sized display devices without compromising performance
2Manufacturing precision
If low-temperature polycrystalline thin film transistors are used to achieve higher resolution, then display quality is improved, but the ability to fabricate large-sized devices is limited
Solution Approach 1:
The patent changes the semiconductor material parameter from polycrystalline silicon to metal oxide, which enables simultaneous achievement of high resolution and large device size. Metal oxide thin film transistors can be fabricated with precise control over a large substrate area using standard deposition techniques, eliminating the size limitations imposed by laser crystallization processes
3Ease of manufacture
If the gate drive circuit structure is simplified, then ease of manufacture is improved, but working performance and output signal quality may deteriorate
Solution Approach 1:
The patent changes the transistor type parameter to metal oxide thin film transistors, which inherently provide excellent electrical characteristics including low off-state current and high mobility. This material parameter change enables the use of simplified circuit structures that can be easily manufactured while maintaining high output signal quality and reliable performance
Solution Approach 2:
The patent designs a universal shift register unit structure using metal oxide thin film transistors that can be applied to various display device sizes and resolutions. The standardized circuit design simplifies manufacturing while the superior transistor characteristics ensure consistent output signal quality across different applications
Data Source
AI summary
A shift register unit including an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node, a first control circuit electrically connected to the first node and a second node and configured to receive the first clock signal to control a voltage of the second node, an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal, an output voltage control circuit electrically connected to the second node and the output terminal and configured to control a voltage of the output signal, and a discharge circuit electrically connected to the first node and the second node and configured to receive the second clock signal to achieve electrical discharge of the first node.