Metal Oxide TFT Dopant Layer for Low-Leakage Interface Stability
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Solution Overview
Problem
Metal oxide semiconductor transistors, particularly thin-film transistors, face issues with leakage current and instability due to oxygen vacancies and chemical reactions at the active layer-gate dielectric interface, leading to high contact resistance and sensitivity to thermal and electrical stress.
Innovation Solution
Integration of n-type dopants, electrically neutral dopants, and a high-k dielectric cap passivation layer into metal oxide semiconductor transistors to reduce leakage current, stabilize the device under electrical bias and thermal cycling, and enhance charge carrier concentration by passivating oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal oxide semiconductor transistors are used for low-temperature processing, then compatibility with previously fabricated devices is improved, but leakage current and instability increase due to oxygen vacancies and chemical reactions at the interface
Solution Approach 1:
A dopant layer is introduced as an intermediary between the gate dielectric layer and the active layer. This dopant layer serves as a mediator that prevents direct harmful chemical reactions at the interface while enabling controlled dopant diffusion into the active layer to improve electrical stability and reduce leakage current.
Solution Approach 2:
The dopant layer is formed in advance before final device operation. By pre-positioning dopants in the dopant layer, the structure is prepared to release dopants into the active layer under controlled conditions, preventing oxygen vacancies and interface reactions before they can cause reliability issues.
2Quantity of substance
If dopants are introduced into the active layer, then charge carrier concentration is improved, but oxygen vacancies and chemical reactions at the interface increase
Solution Approach 1:
The dopant layer acts as an intermediary reservoir that separates the dopant introduction process from the active layer. Dopants diffuse from the dopant layer into the active layer in a controlled manner, achieving high charge carrier concentration without direct introduction that would cause oxygen vacancies and harmful chemical reactions at the gate dielectric interface.
3Reliability
If a dopant layer is inserted between the gate dielectric layer and the active layer, then dopant diffusion is controlled and interface reactions are reduced, but device structure becomes more complex
Solution Approach 1:
The dopant layer is positioned locally at the critical interface region between the gate dielectric and active layer, where it is most needed to prevent harmful reactions. This localized approach provides maximum benefit with minimal added complexity, as the dopant layer only occupies the specific region where interface protection is required.
4Manufacturing precision
If multiple dopant sources are used, then dopant concentration profile is enhanced, but manufacturing process becomes more complex
Solution Approach 1:
The dopant layer is formed in advance as a pre-prepared dopant reservoir using standard thin film deposition techniques. This preliminary action consolidates multiple dopant sources into a single layer that can be formed in one processing step, simplifying manufacturing while enabling controlled dopant diffusion to achieve the desired concentration profile in the active layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current, improves electrical and thermal stability, and enhances overall device performance by modifying the chemical states at the interface and reducing oxygen deficiencies, resulting in improved contact resistance and carrier concentration.
Implementation Method 1
a dopant layer inserted between the gate dielectric layer and the active layer to facilitate dopant diffusion
Implementation Method 2
reduce leakage current, stabilize the device under electrical bias and thermal cycling, and enhance charge carrier concentration by passivating oxygen vacancies
Data Source
AI summary
A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.