Metal Pad Impurity Gradient for Semiconductor Bonding Flatness

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Solution Overview

Problem

In semiconductor storage devices, particularly three-dimensional memories, dishing during metal pad polishing leads to defective bonding between wafers due to recessed surfaces, resulting in gaps at the bonding interface.

Innovation Solution

Introducing carbon, silver, or silicon as impurities into the metal pads and performing a thermal treatment to increase their volume and create a concentration gradient, ensuring flat surfaces and preventing gaps during bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If metal pads are polished to ensure flat surfaces for bonding, then bonding quality improves, but dishing occurs causing recessed surfaces and gaps at the bonding interface

Engineering Contradiction:
Improveflatness of metal pad surfaceVSAvoiddishing of metal pad surface
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent introduces impurities into the metal pad before bonding and performs preliminary thermal treatment to increase volume and create concentration gradient. This preliminary action compensates for potential dishing before the actual bonding process, ensuring the surface remains sufficiently flat for quality bonding without excessive polishing that would cause dishing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical and chemical parameters of the metal pad by introducing impurities (carbon, silver, or silicon) and performing thermal treatment. This alters the volume and concentration distribution of the metal pad, creating a concentration gradient that prevents dishing while maintaining surface flatness for bonding.

Inventive Principle:
Principle #35Parameter changes

2Shape

If thermal treatment is performed to increase metal pad volume and create concentration gradient, then dishing is prevented and surface flatness improves, but additional processing steps are required

Engineering Contradiction:
Improveflatness of metal pad surfaceVSAvoidnumber of processing steps
Core Design Contradiction:
ShapeVSDevice complexity

Solution Approach 1:

The patent combines the impurity introduction step with the existing metal pad formation process, and integrates the thermal treatment with other thermal processing steps in the manufacturing flow. By merging these operations with existing process steps, the additional complexity is minimized while still achieving the volume increase and concentration gradient necessary to prevent dishing.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces defective bonding between array and circuit chips by ensuring the metal pads are uniformly flat, enhancing the bonding process and preventing gaps at the interface.

Implementation Method 1

performing a thermal treatment to increase their volume and create a concentration gradient

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11322441B2Semiconductor storage device including a memory cell array and manufacturing method of the same
Publication Date: 2022.05.03 KIOXIA CORP
  • US11322441B2 patent drawing
  • US11322441B2 patent drawing
  • US11322441B2 patent drawing

AI summary

A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.