Metal Resistive Element Layer for Oscillator Frequency Stability
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Solution Overview
Problem
In microcomputer products with integrated on-chip oscillators, polysilicon resistors used in high-speed OCO circuits face significant resistance value fluctuations due to piezo resistance effects, particularly mold stress during packaging, leading to precision issues in achieving the target oscillation frequency of 40 MHz±1%. Existing solutions complicate the manufacturing process and increase costs by requiring separate masks for forming conductive layers connected to resistors and wiring layers.
Innovation Solution
A semiconductor device design featuring a metal resistive element layer positioned below the second wiring layer, with conductive layers extending perpendicularly to connect both, allowing for simultaneous formation of conductive layers for the resistor and wiring layers using the same mask, reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon resistor is used in the high-speed OCO circuit, then the circuit can be implemented with conventional processes, but the resistance value fluctuates significantly due to piezo resistance effect from mold stress, making it difficult to achieve target precision of 40 MHz±1%
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal (such as aluminum or copper) to eliminate the piezo resistance effect that causes resistance value fluctuation in polysilicon resistors under mold stress, thereby achieving stable oscillation frequency within 40 MHz±1% precision
Solution Approach 2:
The patent uses metal wiring layers that are typically used for interconnect purposes as resistive elements, replacing dedicated polysilicon resistor structures. This approach uses readily available metal layers without requiring additional specialized resistor fabrication processes, simplifying manufacturing while achieving the desired precision
2Area of stationary object
If the resistor is formed on the uppermost layer of the multilayer wiring structure, then the layout area is reduced, but the resistor is directly covered with protective film and likely to receive stress, causing resistance value variation
Solution Approach 1:
The patent positions the metal resistive element layer at a different vertical position within the multilayer wiring structure, specifically using metal layers that are not the uppermost layer. This dimensional repositioning allows the resistive element to be surrounded by insulating films on all sides, protecting it from stress while maintaining compact layout
3Manufacturing precision
If separate masks are used to form conductive layers for the resistor and for wiring layers, then electrical connections can be precisely controlled, but the manufacturing process becomes complicated and manufacturing cost increases
Solution Approach 1:
The patent merges the formation of conductive layers for both resistor connections and wiring layer connections into a single mask process. By positioning the metal resistive element layer within the existing multilayer wiring structure and using the same mask to define both resistor and wiring conductive layers, the patent eliminates the need for separate masking steps, reducing manufacturing complexity while maintaining connection precision
Solution Approach 2:
The patent makes the metal wiring layers serve dual functions: as interconnect wiring and as resistive elements for the OCO circuit. This multi-functionality allows a single mask design to define both the wiring pattern and the resistive element pattern, eliminating the need for dedicated resistor masks and simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the likelihood of resistance value fluctuations, enhances the reliability of the metal resistive element layer, and simplifies the manufacturing process by eliminating the need for separate masks, thereby improving the precision and cost-effectiveness of the high-speed OCO circuit.
Implementation Method 1
as for the polysilicon resistor, its resistance value is fluctuated by a stress due to a piezo resistance effect
Data Source
AI summary
A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.