Metal-Semiconductor Alloy Interconnections for 3D ICs
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Solution Overview
Problem
The challenge in 3D integrated circuits is to create interconnection elements with improved performance while adhering to relaxed thermal budget constraints, as existing metal interconnections degrade at elevated temperatures.
Innovation Solution
A method involving the formation of semiconducting material elements through insulating layers, followed by thermal annealing to create metal-semiconductor alloys like NiSi or CoSi2, which allows for lower thermal budget compatibility and reduced resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnections (such as W) are used to connect different transistor levels, then electrical conduction is achieved, but the interconnections degrade when exposed to temperatures above 400°C-500°C
Solution Approach 1:
The patent changes the material parameter of the interconnection from pure metal (W) to a metal-semiconductor composite structure. The semiconducting material (silicon) is deposited to fill the opening, and through thermal annealing, a metal-semiconductor alloy is formed that maintains electrical conductivity while withstanding higher temperatures without degradation.
Solution Approach 2:
The patent creates a composite interconnection structure by combining metal (tungsten) and semiconducting material (silicon) within the same interconnection element. This composite approach allows the interconnection to benefit from both the electrical conductivity of metal and the thermal stability of semiconductor, resolving the contradiction between conductivity and temperature resistance.
2Reliability
If the thermal budget is limited to 500°C to protect metal interconnections, then interconnection damage is avoided, but fabrication processes requiring higher temperatures cannot be performed
Solution Approach 1:
The patent performs the high-temperature fabrication processes (above 500°C) before forming the metal-semiconductor interconnection structure. By establishing the interconnection with thermally stable materials first, subsequent high-temperature processing steps can be executed without risking interconnection damage, thereby enabling fabrication flexibility while maintaining interconnection integrity.
3Reliability
If conventional metal interconnections are used, then electrical conduction is provided, but the critical dimensions must be larger to maintain acceptable resistivity
Solution Approach 1:
The patent employs a metal-semiconductor composite structure where the semiconducting material (silicon) forms an integral part of the interconnection. This composite approach enables the interconnection to achieve lower resistivity at smaller critical dimensions compared to conventional metal interconnections, as the metal-semiconductor alloy provides enhanced electrical conduction properties in nanoscale dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of connection elements with lower resistivity and smaller critical dimensions, specifically less than 10 nm, while avoiding damage from high temperatures, thus enhancing the performance of 3D integrated circuits.
Implementation Method 1
deposit a metallic layer on the element and perform at least one thermal annealing so as to form a connection element made of an alloy of the metal and the semiconducting material
Data Source
AI summary
Fabrication of an integrated circuit comprising:at least one first transistor made at least partially in a first semiconducting layer,at least one second transistor made at least partially in a second semiconducting layer formed above the first semiconducting layer,an insulating layer formed between the first transistor and the second transistor, one or several connection elements passing through the insulating layer between the first and the second transistor,at least one connection element being connected to the first and/or the second transistor and being based on a metal-semiconductor alloy.