Metal Silicide Layer Formation on Polysilicon Patterns
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration and performance due to increased electrical resistance of conductive patterns, making it difficult to realize fine structures and maintain desired properties.
Innovation Solution
A production method involving the formation of a metal silicide layer by depositing a silicon seed layer on a polysilicon pattern, followed by a metal layer, and subsequent heat treatment, with pre-treatment using hydrogen radical solutions to minimize voltage loss and stabilize the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the design rule is decreased to realize fine structure, then the integration level is improved, but the electrical resistance of conductive pattern increases
Solution Approach 1:
The patent changes the material composition and structural parameters of the conductive pattern by forming a metal silicide layer over the polysilicon pattern. This material parameter change reduces electrical resistance while maintaining the fine structure dimensions, resolving the contradiction between manufacturing precision and electrical resistance.
Solution Approach 2:
The patent creates a composite conductive structure consisting of polysilicon pattern combined with metal silicide layer. This composite material approach leverages the low resistance properties of metal silicide to compensate for the high resistance inherent in fine-structure polysilicon patterns, thereby reducing overall electrical resistance while maintaining fine structure geometry.
2Reliability
If a metal silicide layer is formed to cover the polysilicon pattern, then the electrical resistance is reduced, but the process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the polysilicon pattern first with exposed regions, then selectively forming the silicon seed layer and subsequent metal silicide layer. This sequential preliminary action approach systematically reduces resistance while managing process complexity through staged fabrication steps.
Solution Approach 2:
The patent introduces a silicon seed layer as an intermediary between the polysilicon pattern and the metal layer. This intermediary layer facilitates controlled formation of the metal silicide layer, enabling resistance reduction while managing process complexity through a mediating fabrication step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method minimizes voltage loss and ensures stable program/erase properties in non-volatile memory devices by forming a metal silicide layer that covers the polysilicon pattern, reducing power drop and maintaining device stability with minimal power consumption.
Implementation Method 1
bonding a hydrogen atom onto the insulating layer and the polysilicon pattern that are exposed to the substrate
Implementation Method 2
supplying one or more source gases selected from a group including SiH4, Si2H6, Si3H8 and Si4H10 to the inside of a chamber
Implementation Method 3
forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed
Implementation Method 4
forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed
Data Source
AI summary
Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.