Metal Strip Flip-Chip Packaging for Low-Parasitic Semiconductor Packages

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Solution Overview

Problem

Semiconductor devices are highly sensitive to parasitic electrical effects such as parasitic interconnect resistance and inductance, which existing methods to reduce often result in higher costs, larger package size, and reduced device performance.

Innovation Solution

A method involving a metal strip for flip chip bonding, where semiconductor dies are mounted in a flip chip arrangement, encapsulated with an insulating material, and package terminals are formed from the metal strip or deposited metal, reducing parasitic effects and package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional packaging methods are used to reduce parasitic electrical effects, then parasitic resistance and inductance are reduced, but package size increases and manufacturing cost increases

Engineering Contradiction:
Improveparasitic electrical effectsVSAvoidpackage size
Core Design Contradiction:
Object-affected harmful factorsVSVolume of stationary object

Solution Approach 1:

The patent merges the substrate and package leadframe into a single integrated metal strip structure. The metal strip serves dual functions as both the substrate for mounting semiconductor dies and the package leadframe providing external electrical connections. This integration eliminates the need for separate substrate and leadframe components, reducing overall package size while maintaining low parasitic electrical effects through direct electrical pathways.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal strip performs multiple functions simultaneously: it acts as the substrate for die mounting, provides the package leadframe for external connections, and serves as the electrical interconnect structure. This multi-functionality reduces the number of separate components needed, thereby reducing package size and manufacturing complexity while maintaining electrical performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Object-affected harmful factors

If conventional packaging methods are used to reduce parasitic electrical effects, then parasitic resistance and inductance are reduced, but manufacturing cost increases

Engineering Contradiction:
Improveparasitic electrical effectsVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The integration of substrate and leadframe into a single metal strip reduces the number of assembly steps and components. This simplification lowers manufacturing complexity and cost while maintaining the electrical performance benefits of reduced parasitic effects.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the physical state and configuration of the metal strip through various processing steps including forming, cutting, and shaping to create the final package structure. These parameter changes enable the metal strip to transition from a simple strip to a complex integrated structure with low parasitic effects, achieving high performance through material utilization rather than adding expensive components.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If flip chip arrangement is used with metal strip, then parasitic electrical connections are reduced and package size is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveparasitic electrical connectionsVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The metal strip is pre-formed with specific geometric configurations and electrical connection patterns before semiconductor dies are mounted. This preliminary structuring of the substrate/leadframe integration simplifies subsequent assembly steps, as the electrical pathways are already established, reducing overall manufacturing process complexity despite the advanced flip chip technique used.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12550751B2Flip chip bonding for semiconductor packages using metal strip
Publication Date: 2026.02.10 INFINEON TECHNOLOGIES AG
  • US12550751B2 patent drawing
  • US12550751B2 patent drawing
  • US12550751B2 patent drawing

AI summary

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.